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參數(shù)資料
| 型號(hào)： | HDMP-1514 |
| 英文描述： | Fibre Channel Receiver Chipset(光纖通道接收芯片) |
| 中文描述： | 光纖信道接收芯片（光纖通道接收芯片） |
| 文件頁(yè)數(shù)： | 8/26頁(yè) |
| 文件大小： | 284K |
| 代理商： | HDMP-1514 |
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8
HDMP-1512 (Tx), HDMP-1514 (Rx)
Specified Operating Rates
T
C
= 0
°
C to +85
°
C, V
CC
= 4.5 V to 5.5 V
Transmit Byte Clock (TBC)
(MHz)
Min.
52.0
52.0
Serial Baud Rate
(MBaud/sec)
Min.
520
1040
SPDSEL
0
1
Max.
54.0
54.0
Max.
540
1080
HDMP-1512 (Tx), HDMP-1514 (Rx)
Absolute Maximum Ratings
Operation in excess of any one of these conditions may result in permanent damage.
Symbol
V
CC
V
IN,TTL
V
IN,H50
I
O,TTL
T
stg
T
J
T
max
Parameter
Units
V
V
V
mA
°
C
°
C
°
C
Min.
-0.5
-0.7
V
CC
- 2.0
Max.
6.0
V
CC
+ 0.7
V
CC
+ 0.7
13
+130
+130
+260
Supply Voltage
TTL Input Voltage
I-H50 Input Voltage, Figure 9
TTL Output Source Current
Storage Temperature
Junction Operating Temperature
Maximum Assembly Temperature (for 10 seconds
maximum)
-40
0
0
Recommended Handling
Precautions
Additional circuitry is built into the
various input and output pins on
these chips to protect them against
low level electrostatic discharge,
however, they are still ESD
sensitive and standard procedures
for static sensitive devices should
be used in the handling and
assembly of the HDMP-1512 and
the HDMP-1514. The packing
materials used for shipment of
these devices was selected to
provide ESD protection and to
prevent mechanical damage.
During test and use, under power-
up conditions, extreme care should
be taken to prevent the high speed
I/Os from being connected to
ground as permanent damage to
the device is likely.
Rx Power Supply
Supervisor
A power supply supervisor feature
has been designed into the
receiver as a system aid during
power-up. The -POR (pin # 27)
output is held low until the power
supply voltage (V
CC
) crosses the
nominal threshold of 4.25 volts.
Then, following a delay time
determined by the capacitor value
connected to the PS_CT pin
(# 22), the -POR output goes high.
The typical delay time is 8 msec,
with a 0.47
μ
F capacitor attached
to PS_CT.
L
p
0
0
DR_REF VOLTAGE – V
1.0
90
60
40
20
10
0.5
2.5
80
50
1.5
2.0
70
30
DEFAULT
THRESHOLD
Figure 8. Typical Plot of Loss of Light
Threshold Voltage vs. DR_REF
Voltage.
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PDF描述 |
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| HDMP-1526 | Transistor Diode Kit;Contents Of Kit:Transistor/Diode Kit |
| HDMP-1536 | Fibre Channel Transceiver Chip |
| HDMP-1546 | Fibre Channel Transceiver Chip |
| HDMP-1546A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| HDMP-1536A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP1526 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
| HDMP-1526 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
| HDMP-1536 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
| HDMP-1536A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fiber-Optic Transceiver |
| HDMP-1546 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
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