參數(shù)資料
型號(hào)： HDMP-1514
英文描述： Fibre Channel Receiver Chipset(光纖通道接收芯片)
中文描述： 光纖信道接收芯片（光纖通道接收芯片）
文件頁(yè)數(shù)： 18/26頁(yè)
文件大?。?/td> 284K
代理商： HDMP-1514
18
HDMP-1514 (Rx), Signal Definitions (cont’d.)
Symbol
DR_REF
Signal Name
Receiver Reference
Pin [21]
Enable Comma Detect
Pin [38]
I/O
C
Logic Type
Description
This node is used to set the peak-to-peak signal level
of the loss of light detection circuitry.
When high, the receiver will reset internal clocks and
registers when an incoming comma character (K28.5)
of positive disparity (0011111xxx) is detected. When
low, clocks and registers will not reset and the comma
detect output is disabled. Comma detect is also disabled
whenever -LCK_REF is set low.
When set low, the internal cable equalizer amplifier on
the
±
DI lines is enabled.
When set high, the high speed data is taken from the
±
LIN port, enabling the data input from the local
transmitter. When this input is set low, the high speed
input is taken from the
±
DI lines.
Normally 0 volts. Used to provide a clean ground plane
for the critical PLL and high speed analog cells.
Normally 0 volts.
EN_CDET
Input
TTL
-EQEN
Equalizer Enable Input
Pin [32]
Enable Wrap
Pin [71]
Input
TTL
EWRAP
Input
TTL
GND_A
Analog Ground
Pins [3,4]
High Speed Ground
Pins [14,25,26]
Logic Ground
Pins[31,35,70,74]
S
GND_HS
S
GND_LOG
S
Normally 0 volts. Used for all internal PECL logic.
Should be completely isolated from the noisy TTL
ground.
Normally 0 volts. Used for all TTL I/O buffer cells.
GND_TTL
TTL Ground
Pins [39,40,65,66]
TTL Ground
Pin [9]
Lock to Reference
Pin [36]
S
GND_TTLA
S
Normally 0 volts.
-LCK_REF
Input
TTL
A low input causes the internal PLL to acquire
frequency lock on the external reference signal applied
at CLKIN. To assure lock, this pin should be held low
for at least 500
μ
sec and held high at all other times. A
low input disables the comma detect function.
Typically supplied from open fiber control circuitry.
Used in conjunction with EWRAP and -LCK_REF to
keep the internal Vco near operational frequency,
optimizing frequency lock times.
High speed data port, typically connected to the
±
LOUT
port on the local transmitter when in serial wrap mode.
A high signal on this pin indicates the amplitude of
the input serial data has fallen below a preset level
(see DR_REF) or no transitions have been detected
within 4 cycles of TBC.
A high signal on this pin indicates the amplitude of
the input serial data has fallen below a preset level
(see DR_REF) or no transitions have been detected
within 4 cycles of TBC.
Used in conjunction with pin 8 (P_RXTEMP) to
monitor the on-chip temperature diode (Cathode.)
Used in conjunction with pin 6 (N_RXTEMP) to
monitor the on-chip temperature diode (Anode.)
Active low output. Monitors the power supply voltage
on startup to assure V
CC
is at the proper DC level.
L_UNUSE
Link Unusable
Pin [73]
Input
TTL
±
LIN
Local Serial Data
Pins [16,17]
Loss of Light
Signal
Pin [28]
Input
H50
LOLA
Output
TTL
LOLB Loss of Light
Output
TTL
Signal
Pin [29]
N_RXTEMP
Temperature Monitor
Pin [6]
Temperature Monitor
Pin [8]
Power on Reset
Pin [27]
C
P_RXTEMP
C
-POR
Output
TTL
相關(guān)PDF資料
PDF描述
HDMP-1526 Transistor Diode Kit;Contents Of Kit:Transistor/Diode Kit
HDMP-1536 Fibre Channel Transceiver Chip
HDMP-1546 Fibre Channel Transceiver Chip
HDMP-1546A Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片)
HDMP-1536A Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HDMP1526 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
HDMP-1526 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip
HDMP-1536 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip
HDMP-1536A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fiber-Optic Transceiver
HDMP-1546 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip
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