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參數(shù)資料
| 型號： | HDMP-1514 |
| 英文描述： | Fibre Channel Receiver Chipset(光纖通道接收芯片) |
| 中文描述： | 光纖信道接收芯片（光纖通道接收芯片） |
| 文件頁數(shù)： | 19/26頁 |
| 文件大?。?/td> | 284K |
| 代理商： | HDMP-1514 |
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19
HDMP-1514 (Rx), Signal Definitions (cont’d.)
Symbol
PPSEL
Signal Name
Ping-Pong Select
Pin [76]
I/O
Input
Logic Type
TTL
Description
A high input instructs the receiver to clock the data
out in ping-pong mode. Byte 0 will be clocked out on
the falling edge of RBC0 and byte 1 will be clocked out
on the falling edge of RBC1. A low input instructs the
receiver to clock both data bytes out on the falling edge
of RBC0.
Pin for connecting the timing capacitor for the power
supervisor circuit.
PS_CT
Power Supply Timing
Cap
Pin [22]
Receive Byte Clocks
Pin [67, 69]
C
RBC[0:1]
Output
TTL
Two clocks, 180
°
out of phase, generated from the
recovered data. Used to clock out the two 10 bit data
bytes.
Two, 10 bit, bytes. Byte 0 is comprised of bits
RX[00:09] and byte 1 is comprised of bits RX[10:19].
The serialized bit stream is received TX[00] through
TX[09] then TX[10] through TX[19].
Sets the chip to operate at the serial data rate of 1062.5
Mbaud (high) or 531.25 Mbaud (low).
An applied low selects CLKIN as the serial/bit-rate clock
and bypasses the internal PLL. Used for testing only.
Provides a clean power source for the critical PLL
and high speed analog cells. Normally +5.0 volts.
Provides a clean power source for the high speed
receiver cell I-H50. Noise on this line should be
minimized for best performance. Normally +5.0 volts.
Provides a clean power source for the high speed
receiver cell I-H50. Noise on this line should be
minimized for best performance. Normally +5.0 volts.
Used for all internal PECL logic. Isolate from the
noisy TTL supply. Normally +5.0 volts.
Power supply for all TTL buffer I/O cells. Normally
+5.0 volts.
Power supply for all TTL I/O buffer cells. Normally
+5.0 volts.
No connection.
RX[00:19]
Data Outputs
Pins [43, 62]
Output
TTL
SPDSEL
Serial Speed Select
Pin [71]
Test Clock Select
Pin [5]
Analog Supply
Pins [77, 78]
High Speed Supply
Pins [13,23,24]
Input
TTL
-TCLKSEL
Input
TTL
VCC_A
S
VCC_HS1
S
VCC_HS2
High Speed Supply 2
Pins [15,18]
S
VCC_LOG
Logic Power Supply
Pins [33,37,68,72]
TTL Power Supply
Pins [41,42,63,64]
TTL Power Supply
Pin [10]
Pins [11,12,30]
S
VCC_TTL
S
VCC_TTLA
S
NC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-1526 | Transistor Diode Kit;Contents Of Kit:Transistor/Diode Kit |
| HDMP-1536 | Fibre Channel Transceiver Chip |
| HDMP-1546 | Fibre Channel Transceiver Chip |
| HDMP-1546A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| HDMP-1536A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP1526 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
| HDMP-1526 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
| HDMP-1536 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
| HDMP-1536A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fiber-Optic Transceiver |
| HDMP-1546 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
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