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參數(shù)資料
| 型號(hào)： | HDMP-0440 |
| 英文描述： | Voltage Regulator IC; Output Current:100mA; Output Voltage:6.2V; Package/Case:3-TO-92; Voltage Regulator Type:Positive Voltage; Mounting Type:Through Hole; Supply Voltage:35V |
| 中文描述： | 四端口旁路電路的光纖通道仲裁環(huán)路 |
| 文件頁(yè)數(shù)： | 2/10頁(yè) |
| 文件大?。?/td> | 271K |
| 代理商： | HDMP-0440 |
2
HDMP-0440 Block Diagram
BLL OUTPUT
All TO_NODE[n]
±
high-speed
differential outputs are driven by
a Buffered Line Logic (BLL)
circuit that has on-chip source
termination, so no external bias
resistors are required. The BLL
Outputs on the HDMP-0440 are
of equal strength and can drive
lengthy FR-4 PCB trace.
Unused outputs should not be left
unconnected. Ideally, unused
outputs should have their
differential pins shorted together
with a short PCB trace. If longer
traces or transmission lines are
connected to the output pins, the
lines should be differentially
terminated with an appropriate
resistor. The value of the
termination resistor should match
the PCB trace differential
impedance.
EQU INPUT
All FM_NODE[n]
±
high-speed
differential inputs have an
Equalization (EQU) buffer to
offset the effects of skin loss and
dispersion on PCBs. An external
termination resistor is required
across all high-speed inputs. The
value of the termination resistor
should match the PCB trace
differential impedance.
Alternatively, instead of a single
resistor, two resistors in series,
with an AC ground between them,
can be connected differentially
across the FM_NODE[n]
±
inputs.
The latter configuration
attenuates high-frequency
common mode noise.
BYPASS[n]- INPUT
The active low BYPASS[n]- inputs
control the data flow through the
HDMP-0440. All BYPASS pins are
LVTTL and contain internal pull-
up circuitry. To bypass a port,
the appropriate BYPASS[n]- pin
should be connected to GND
through a 1 k
resistor.
Otherwise, the BYPASS[n]- inputs
should be left to float, as the
internal pull-up circuitry will
force them high.
Figure 1. Block diagram of HDMP-0440.
F
T
B
1
0
T
F
T
1
0
F
T
1
0
F
T
1
0
BLL
EQU
TTL
B
BLL
EQU
TTL
B
BLL
EQU
TTL
B
BLL
EQU
TTL
BLL
F
EQU
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|---|---|
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