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參數(shù)資料
| 型號(hào)： | HDMP-0440 |
| 英文描述： | Voltage Regulator IC; Output Current:100mA; Output Voltage:6.2V; Package/Case:3-TO-92; Voltage Regulator Type:Positive Voltage; Mounting Type:Through Hole; Supply Voltage:35V |
| 中文描述： | 四端口旁路電路的光纖通道仲裁環(huán)路 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 271K |
| 代理商： | HDMP-0440 |
Agilent HDMP-0440
Quad Port Bypass Circuit
for Fibre Channel Arbitrated Loops
Data Sheet
Features
Supports 1.0625 GBd Fibre
Channel operation
Supports 1.25 GBd Gigabit
Ethernet (GE) operation
Quad PBC in one package
Equalizers on all inputs
High-speed LVPECL I/O
Buffered Line Logic (BLL) outputs
(no external bias resistors
required)
0.5 W typical power at V
CC
= 3.3 V
44 Pin, 10 mm, low-cost plastic
QFP package
Applications
RAID, JBOD, BTS cabinets
Two 2:1 muxes
Two 1:2 buffers
1
≥
N Gigabit serial buffer
N
≥
1 Gigabit serial mux
Description
The HDMP-0440 is a Quad Port
Bypass Circuit (PBC), which
provides a low-cost, low-power
physical-layer solution for Fibre
Channel Arbitrated Loop (FC-AL)
disk array configurations. By using
a PBC such as the HDMP-0440,
hard disks may be pulled out or
swapped while other disks in the
array are available to the system.
A PBC consists of multiple 2:1
multiplexers daisy chained
together. Each port has two modes
of operation: “disk in loop” and
“disk bypassed.” When the “disk in
loop” mode is selected, the loop
goes into and out of the disk drive
at that port. For example, data goes
from the HDMP-0440’s
TO_NODE[n]
±
differential output
pins to the Disk Drive Transceiver
IC’s (e.g. an HDMP-1636A) Rx
differential input pins. Data from
the Disk Drive Transceiver IC’s Tx
differential outputs goes to the
HDMP-0440’s FM_NODE[n]
±
differential input pins. Figure 2
shows connection diagrams for
disk drive array applications.
When the “disk bypassed” mode
is selected, the disk drive is either
absent or non-functional and the
loop bypasses the hard disk.
The “disk bypassed” mode is
enabled by pulling the
BYPASS[n]- pin low. Leave
BYPASS[n]- floating to enable the
“disk in loop” mode. HDMP-
0440s may be cascaded with
other members of the HDMP-
04XX/HDMP-05XX family
through the appropriate
FM_NODE[n]
±
and
TO_NODE[n]
±
pins to
accommodate any number of
hard disks (see Figure 3). The
unused cells in the HDMP-0440
may be bypassed by using
pulldown resistors on the
BYPASS[n]- pins for these cells.
An HDMP-0440 may also be
configured as five 1:1 buffers, as
two 2:1 multiplexers or as two
1:2 buffers.
CAUTION:
As with all semiconductor ICs, it is advised that normal static precautionsb be taken in
the handling and assembly of this component to prevent damage and/or degradation which may be
induced by electrostatic discharge (ESD).
HDMP-0440
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-0450 | 制造商:Agilent Technologies 功能描述: |
| HDMP-0451 | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0451G | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0452 | 制造商:AGILENT 制造商全稱(chēng):AGILENT 功能描述:Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops |
| HDMP-0480 | 制造商:AGILENT 制造商全稱(chēng):AGILENT 功能描述:Octal Cell Port Bypass Circuit without Clock and Data Recovery |
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