- 您現在的位置：買賣IC網 > PDF目錄384397 > HDM8515P (Hynix Semiconductor Inc.) Operational Amplifier (Op-Amp) IC; Number of Amplifiers:4; Package/Case:14-DIP; Op Amp Type:Low Power; Single Supply Voltage Min (+V):3V; Dual Supply Voltage Max (+/- V):16V; Amplifier Type:Operational; Mounting Type:Through Hole PDF資料下載
參數資料
| 型號： | HDM8515P |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | Operational Amplifier (Op-Amp) IC; Number of Amplifiers:4; Package/Case:14-DIP; Op Amp Type:Low Power; Single Supply Voltage Min (+V):3V; Dual Supply Voltage Max (+/- V):16V; Amplifier Type:Operational; Mounting Type:Through Hole |
| 中文描述： | 的DVB /決策支持系統兼容接收器 |
| 文件頁數： | 54/75頁 |
| 文件大?。?/td> | 272K |
| 代理商： | HDM8515P |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁當前第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁
54
Bit 4. This bit should be fixed to zero
Bit 5. Regulated Data Clock
Enables/Disables the data and data clock regulator. When this bit is set
to 1, data output and data clock are regulated by FIFO operation. When
this bit is set to 0, internal data output and internal data clock are by-
passed
Bit 6. This bit should be fixed to zero.
Bit 7. Clock Polarity
This bit is used to select the DATA_CLK polarity either for serial or
parallel transport interface. If this bit is set to zero(default value)
,
the
transport data and control signals are latched at the positive edge of
DATA_CLK. Otherwise, the signals are latched at the negative edge of
DATA_CLK.
Viterbi Lock Threshold
Register 15 to 17 contain control parameters for synchronization in
Viterbi decoder. Ordinary users are recommended to use the default
value.
Bit[7:4] defines the lock threshold for VB_NODESYNC. Viterbi decoder
decides that the correct code rate has been found. A large number
means it takes longer to find the correct code rate in automatic
detection mode. It should be greater than 7. The default value is 12.
Bit[3:0] defines the lock fail threshold. Viterbi decoder rejects a code
rate and moves on to the next code rate. A small number means Viterbi
decoder tries more data before it moves to the next code rate. It should
be less than 7. The default value is 2.
Viterbi Unlock Threshold
This number defines the threshold to maintain the Viterbi lock state. A
large number means it needs more bad data to get out of the viterbi lock
state and re-start searching the correct code rate. The default value is
1.
15
16
相關PDF資料 |
PDF描述 |
|---|---|
| HE6SF200 | High efficiency super fast silicon rectifier diode |
| HE82005 | 8-BIT MICRO-CONTROLLER |
| HE82006 | 8-BIT MICRO-CONTROLLER |
| HE82015 | 8-BIT MICRO-CONTROLLER |
| HE83000 | 8-BIT MICRO-CONTROLLER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HDM9010 | 制造商:SHOULDER 制造商全稱:SHOULDER 功能描述:Frequency Synthesizer |
| HDM9020 | 制造商:SHOULDER 制造商全稱:SHOULDER 功能描述:Frequency Synthesizer |
| HDM9030 | 制造商:SHOULDER 制造商全稱:SHOULDER 功能描述:Frequency Synthesizer |
| HDM9040 | 制造商:SHOULDER 制造商全稱:SHOULDER 功能描述:Frequency Synthesizer |
| HDM9050 | 制造商:SHOULDER 制造商全稱:SHOULDER 功能描述:Frequency Synthesizer |
發(fā)布緊急采購，3分鐘左右您將得到回復。