參數(shù)資料
型號(hào)： HDM8515P
廠商： Hynix Semiconductor Inc.
英文描述： Operational Amplifier (Op-Amp) IC; Number of Amplifiers:4; Package/Case:14-DIP; Op Amp Type:Low Power; Single Supply Voltage Min (+V):3V; Dual Supply Voltage Max (+/- V):16V; Amplifier Type:Operational; Mounting Type:Through Hole
中文描述： 的DVB /決策支持系統(tǒng)兼容接收器
文件頁(yè)數(shù)： 30/75頁(yè)
文件大?。?/td> 272K
代理商： HDM8515P
30
3.7 Clock Generation PLL
An integrated VCO is locked to MxN times a reference frequency provided by a external clock.
1.Determining Output Frequency
Fully programmable feedback and reference divider capability allows virtually any frequency
to be generated, not just simple multiples of reference frequency.
There are two status exist
(1) PLL Disable mode : The PLL is bypassed and the external clock is directly connected to the
Internal clock.
(2) PLL Enable mode : The internal clock is connected to the generated clock of the PLL.
1.1 PLL disable mode
PLL control setting is as follows
TDM (Bit 7 of 0x23 register) is set to one and BYPASS (Bit 4 of 0x23 register) is set to one.
1.2 Normal Frequency mode
Output frequency range is limited to 160MHz.
PLL control setting is as follows:
TDM (Bit 7 of 0x23 register) is set to zero, and BYPASS (Bit 4 of 0x23 register) is set to
zero.
At this condition, the output frequency, F(ck), is actually determined by the following
equation.
F(ck) = ----------------------------------------------
F(ck) : Frequency of output
F(ref): Frequency of reference input
Feedback divisor : M[13:0]+2 , (0x25 and 0x26 registers)
Reference divisor : N[7:0]+1 , (0x27 register)
1.3 Extended Frequency mode
Output frequency range is limited to 320MHz.
PLL control setting is as follows
TDM (Bit 7 of 0x23 register) is set to zero, and BYPASS (Bit 4 fo 0x23 register) is set to
one.
At this condition, the output frequency, F(ck), is actually determined by the following
Equation
F(ck) = --------------------------------------------------------
Pre divisor : 2
2. PLL Control Parameter setting
Besides of M (Feedback divisor), N (Reference divisor), P (Pre divisor) , You must determine vc
(VCO range control vector), lfm (Loop filter mode selector), icp (Charge pump bias current
control
p[1:0]+1
, P is Bit 2 and 3 of 0x23 register
F(ref) x (Feedback divisor)
(Reference divisor)
F(ref) x (Feedback divisor) x (Pre divisor)
(Reference divisor)
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