參數(shù)資料
型號(hào)： HDM8515P
廠商： Hynix Semiconductor Inc.
英文描述： Operational Amplifier (Op-Amp) IC; Number of Amplifiers:4; Package/Case:14-DIP; Op Amp Type:Low Power; Single Supply Voltage Min (+V):3V; Dual Supply Voltage Max (+/- V):16V; Amplifier Type:Operational; Mounting Type:Through Hole
中文描述： 的DVB /決策支持系統(tǒng)兼容接收器
文件頁(yè)數(shù)： 4/75頁(yè)
文件大?。?/td> 272K
代理商： HDM8515P
4
TABLE OF CONTENTS
1. INTRODUCTION TO THE HDM8515...................................................................................................................7
1.1 F
EATURES AND
B
ENEFITS
..................................................................................................................................8
2. HARDWARE SPECIFICATION..............................................................................................................................9
3. TECHNICAL OVERVIEW.....................................................................................................................................19
3.1 D
UAL
C
HANNEL
A
NALOG TO
D
IGITAL
C
ONVERTER
..................................................................................19
3.2 V
ARIABLE
R
ATE
D
EMODULATOR
..................................................................................................................21
3.3 N
OISE
M
EASUREMENT
C
IRCUIT
.....................................................................................................................23
3.4 V
ITERBI
D
ECODER
.............................................................................................................................................25
3.5 A
UTONOMOUS
A
CQUISITION
..........................................................................................................................26
3.6 R
EED
S
OLOMON
D
ECODER
..............................................................................................................................28
3.7 C
LOCK
G
ENERATION
PLL.................................................................................................................................30
3.8 DBS R
ECEIVER
...................................................................................................................................................35
3.9 D
I
SE
Q
C I
NTERFACE
...........................................................................................................................................36
4. MECHANICAL SPECIFICATIONS.....................................................................................................................37
4.1 100 P
IN
Q
UAD
F
LAT
P
ACK
................................................................................................................................37
4.2 64 P
IN
T
HIN
Q
UAD
F
LAT
P
ACK
........................................................................................................................39
4.3 R
ECOMMENDED
A
NALOG
P
IN
C
ONNECTION
...............................................................................................41
4.4 R
ECOMMENDED
C
LOCK
G
ENERATION
C
IRCUIT
...........................................................................................41
5. SIGNAL DESCRIPTION....................................................................................................................................... 42
5.1 I
NPUTS
..................................................................................................................................................................42
5.2 O
UTPUTS
.............................................................................................................................................................42
5.3 M
ONITOR AND
C
ONTROL
I
NTERFACE
...........................................................................................................45
5.4 I2C M
ODE
.............................................................................................................................................................46
6. REGISTER DEFINITIONS.....................................................................................................................................48
6.1 W
RITE
R
EGISTERS
..............................................................................................................................................48
6.2 R
EAD
R
EGISTERS
................................................................................................................................................61
APPENDIX....................................................................................................................................................................66
A1. L
OOP
F
ILTER
P
ROGRAMMING
A
PPLICATION
N
OTE
................................................................................67
A2. F
ALSE
L
OCK
E
SCAPE
A
PPLICATION
N
OTE
.................................................................................................70
A3. P
ERFORMANCE WITH
I
NTERFERENCE
..........................................................................................................71
A4. N
YQUIST
C
RITERIA
C
ONSIDERATIONS
.........................................................................................................75
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