參數(shù)資料
型號(hào): HD66728
廠商: Hitachi,Ltd.
英文描述: 112 x 80-dot Graphics LCD Controller/Driver(112 x 80點(diǎn)圖形LCD控制器)
中文描述: 112 × 80點(diǎn)圖形LCD控制器/驅(qū)動(dòng)器(112 × 80點(diǎn)圖形液晶顯示控制器)
文件頁數(shù): 17/138頁
文件大?。?/td> 2158K
代理商: HD66728
HD66728
17
Block Function Description
System Interface
The HD66728 has five types of system interfaces, and a clock-synchronized serial, a 68-system 4-bit/8-bit
bus, and a 80-system 4-bit/8-bit bus. The interface mode is selected by the IM2-0 pins. The key scan of the
HD66728 is not available for the 4-bit/8-bit bus interface. Instead, use the clock-synchronized serial
interface.
The HD66728 has two 8-bit registers: an instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as clear display, display control, and address information for the
display data RAM (DDRAM) and character generator RAM (CGRAM).
The DR temporarily stores data to be written into the DDRAM or CGRAM. Data written into the DR from
the MPU is automatically written into the DDRAM or CGRAM by internal operation. When address
information is written into the IR, data is read and then stored in the DR from the DDRAM or CGRAM by
internal operation. Data is read through the DR when reading from the RAM, and the first read data is
invalid and the second and the following data are normal. After reading, data in the DDRAM or CGRAM
at the next address is sent to the DR for the next reading from the MPU.
Execution time for instruction excluding clear display is 0 clock cycle and instructions can be written in
succession.
Table 3
Register Selection by RS and R/W Bits
R/W Bits
RS Bits
Operations
0
0
Write instructions to IR
1
0
Read key scan data (SCAN0-3)
0
1
DR write as an internal operation (DR to DDRAM or CGRAM)
1
1
DR read as an internal operation (DDRAM or CGRAM to DR)
Key Scan Registers (SCAN0 to SCAN3)
The key matrix scanner senses and holds the key states at each rising edge of the key strobe signals that are
output by the HD66728. The key strobe signals are output as time-multiplexed signals from KST0 to
KST3. After passing through the key matrix, these strobe signals are used to sample the key status on eight
inputs from KIN0 to KIN7, enabling up to 32 keys to be scanned.
The states of inputs KIN0 to KIN7 are sampled by key strobe signal KST0 and latched into register
SCAN0. Similarly, the data sampled by strobe signals KST1 to KST3 is latched into registers SCAN1 to
SCAN3, respectively.
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