
126 HITACHI
H'E000000
H'E400000
H'E800000
H'EC00000
H'E3FFFFF
H'E7FFFFF
H'EBFFFFF
H'EFFFFFF
Shadow
Shadow
Shadow
Shadow
External
memory
space
(4 Mbytes)
H'6000000
H'6400000
H'6800000
H'6C00000
H'63FFFFF
H'67FFFFF
H'6BFFFFF
H'6FFFFFF
Shadow
Shadow
Shadow
Shadow
Multiplexed
I/O space
or external
memory
space
(4 Mbytes)
Logical address
space
Logical address
space
8 or 16-bit
space
16-bit space
Actual
space
Actual
space
IOE = 1:
address/data
multiplexed I/O
space;
IOE = 0: external
memory space
A14 = 0: 8-bit space
A14 = 1: 16-bit space
Valid addresses
A21–A0 (A23 and
A22 not output)
CS6
valid
Long wait function
Valid
addresses
A21–A0 (A23
and A22 not
output)
CS6
valid
Long wait
function
Figure 8.9 Memory Map of Area 6
Area 7:
Area 7 is the area where addresses A26–A24 are 111 and its address range is H'7000000–
H'7FFFFFF and H'F000000–H'FFFFFFF. Figure 8.10 is a memory map of area 7.
Area 7 is allocated to external memory space when A27 is 0 and on-chip RAM space when A27 is
1. In external memory space, the bus width is 8 bits. The A23 and A22 bits are not output and the
shadow is in 4-Mbyte units. When external memory is accessed, the
CS7
signal is valid.
The on-chip RAM space has an bus width of 32 bits. The on-chip RAM capacity is 1 kbytes, so
A23–A10 are ignored and the shadows are in 8-kbyte units. During on-chip RAM access, the
CS7
signal is not valid.