參數(shù)資料
型號: HCS12COREUG
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Device User Guide V01.18
中文描述: 設(shè)備的用戶手冊V01.18
文件頁數(shù): 124/130頁
文件大?。?/td> 512K
代理商: HCS12COREUG
MC9S12H256 Device User Guide — V01.18
32
D NOACC hold time
t
NOH
2
ns
33
D IPIPO[1:0] delay time
t
P0D
2
7
ns
34
D IPIPO[1:0] valid time to E rise (PW
EL
–t
P0D
)
t
P0V
22
ns
35
D IPIPO[1:0] delay time
1
(PW
EH
–t
P1V
)
t
P1D
2
25
ns
36
D IPIPO[1:0] valid time to E fall
t
P1V
22
ns
NOTES
:
1. Affected by clock stretch: add N x t
cyc
where N=0,1,2 or 3, depending on the number of clock stretches.
Table A-20 Expanded Bus Timing Characteristics
Conditions are shown in
Table A-4
unless otherwise noted, C
LOAD
= 50pF
Num C
Rating
Symbol
Min
Typ
Max
Unit
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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