參數(shù)資料
型號： HCS12COREUG
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： Device User Guide V01.18
中文描述： 設備的用戶手冊V01.18
文件頁數(shù)： 110/130頁
文件大小： 512K
代理商： HCS12COREUG
MC9S12H256 Device User Guide — V01.18
The loop bandwidth f
C
should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50.
ζ
= 0.9 ensures a good transient response.
And finally the frequency relationship is defined as
With the above inputs the resistance can be calculated as:
The capacitance C
s
can now be calculated as:
The capacitance C
p
should be chosen in the range of:
The stabilization delays shown in
Table A-15
are dependant on PLL operational settings and external
component selection (e.g. crystal, XFC filter).
A.4.3.2 Jitter Information
The basic functionality of the PLL is shown in
Figure A-2
. With each transition of the clock f
cmp
, the
deviation from the reference clock f
ref
is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise,voltage,temperatureandotherfactorscauseslightvariationsinthecontrolloopresultinginaclock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in
Figure A-3
.
f
C
2
ζ
f
ref
------------------------------------------
π
ζ
1
ζ
2
+
+
1
50
------
f
C
f
ref
4 50
-------------
ζ
0.9
=
(
)
;
<
→
<
n
f
VCO
f
ref
-------------
2
synr
1
+
(
)
=
=
R
2
π
n f
C
K
Φ
----------------------------
=
C
s
2
ζ
2
π
f
C
R
---------------------
0.516
f
C
R
--------------
ζ
0.9
=
(
)
;
≈
=
C
s
20
C
p
C
s
10
≤
≤
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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