參數(shù)資料
型號: HCS12COREUG
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Device User Guide V01.18
中文描述: 設(shè)備的用戶手冊V01.18
文件頁數(shù): 109/130頁
文件大?。?/td> 512K
代理商: HCS12COREUG
A.4.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL′s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.4.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
Figure A-2 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K
1
, f
1
and i
ch
from
Table A-15
.
The VCO Gain at the desired VCO output frequency is approximated by:
The phase detector relationship is given by:
i
ch
is the current in tracking mode.
3. XCLKS =1 during reset
f
osc
1
refdv+1
f
ref
Phase
Detector
VCO
K
V
1
synr+1
f
vco
Loop Divider
K
Φ
1
2
f
cmp
C
s
R
C
p
VDDPLL
K
V
K
1
e
f
K
1
1V
vco
-----------f
)
=
K
Φ
i
ch
K
V
=
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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