參數(shù)資料
型號: HCS12COREUG
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Device User Guide V01.18
中文描述: 設備的用戶手冊V01.18
文件頁數(shù): 115/130頁
文件大?。?/td> 512K
代理商: HCS12COREUG
A.6 SPI
A.6.1 Master Mode
Figure A-5
and
Figure A-6
illustrate the master mode timing. Timing values are shown in
Table A-17
.
SS
1
(OUTPUT)
Figure A-5 SPI Master Timing (CPHA = 0)
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
1
9
5
6
MSB IN
2
BIT 6 . . . 1
LSB IN
MSB OUT
2
LSB OUT
BIT 6 . . . 1
10
4
4
2
9
(CPOL
=
0)
(CPOL
=
1)
3
11
12
1. If configured as output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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