參數(shù)資料
型號: HCPL-7870
英文描述: Isolated 15-bit A/D Converter(隔離15位A/D轉(zhuǎn)換器)
中文描述: 隔離15位A / D轉(zhuǎn)換器(隔離15位的A / D轉(zhuǎn)換器)
文件頁數(shù): 24/30頁
文件大小: 344K
代理商: HCPL-7870
24
Configuration
Data Bits
Bit 3
Low
High
Mode
Off
On
Note:
Bold italic type indicates default
values.
Offset
Calibration
Table 5. Pre-Trigger Mode Configuration.
Configuration Data Bits
Bit 7
Low
Low
High
Pre-Trigger Mode
0
1
2
Bit 6
Low
High
Don’t Care
Note:
Bold italic type indicates default values.
Offset Calibration
The offset calibration circuit can
be used to separately calibrate
the offsets of both channels 1 and
2. The offset calibration circuit
contains a separate offset register
for each channel. After an offset
calibration sequence, the offset
registers will contain a value
equal to the measured offset,
which will then be subtracted
from all subsequent conversions.
A hardware reset (bringing the
RESET pin high for at least
100 ns) is required to reset the
offset calibration registers to
zero.
The following sequence is
recommended for performing an
offset calibration:
1. Select the appropriate channel
using the CHAN pin (low =
channel 1, high = channel 2).
2. Force zero volts at the input of
the selected isolated
modulator.
3. Send a configuration data byte
to the appropriate register for
the selected channel (register
0 for channel 1, register 1 for
channel 2). Bit 3 of the
configuration byte should be
set high to enable offset
calibration mode and bits 4
through 7 should be set to
select conversion mode 1 to
achieve the highest resolution
measurement of the offset.
4. Perform one complete conver-
sion cycle by bringing CS low
until SDAT goes high, indicat-
ing completion of the conver-
sion cycle. Because bit 3 of the
configuration has been set
high, the uncalibrated output
data from the conversion will
be stored in the appropriate
offset calibration register and
will be subtracted from all
subsequent conversions on
that channel. If multiple
conversion cycles are
performed while the offset
calibration mode is enabled,
the uncalibrated data from the
last conversion cycle will be
stored in the offset calibration
register.
5. Send another configuration
byte to the appropriate regis-
ter for the selected channel,
setting bit 3 low to disable
calibration mode and setting
bits 4 through 7 to select the
desired conversion mode for
subsequent conversions on
that channel.
To calibrate both channels,
perform the above sequence for
each channel. The offset
calibration sequence can be
performed as often as needed.
The table below summarizes how
to turn the offset calibration
mode on or off using bit 3 of
configuration registers 0 and 1.
periodic, then the pre-trigger
circuit should be disabled by
selecting pre-trigger mode 0. If
the most time-accurate sampling
of the input signal is desired,
then mode 1 should be selected.
If the shortest possible conver-
sion time is desired, then mode 2
should be selected.
The pre-trigger circuit functions
only with channel 1; the circuit
ignores any convert start signals
while channel 2 is selected with
the CHAN input. This allows
conversions on channel 2 to be
performed between conversions
on channel 1 without affecting
the operation of the pre-trigger
circuit. As long as the convert
start signals are periodic while
channel 1 is selected, then the
pre-trigger circuit will function
properly.
The three different pre-trigger
modes are selected using bits 6
and 7 of register 3, as shown in
Table 5 below.
Table 6. Offset Calibration
Configuration.
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