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參數(shù)資料
| 型號： | HCPL-7870 |
| 英文描述： | Isolated 15-bit A/D Converter(隔離15位A/D轉(zhuǎn)換器) |
| 中文描述： | 隔離15位A / D轉(zhuǎn)換器（隔離15位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 23/30頁 |
| 文件大?。?/td> | 344K |
| 代理商： | HCPL-7870 |
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23
WEIGHTING
FUNCTION
CONVERT START – CS
DATA READY – SDAT
A) PRE-TRIGGER MODE 0
B) PRE-TRIGGER MODE 1
C) PRE-TRIGGER MODE 2
Pre-Trigger Mode
The pre-trigger mode refers to
the operation of a PLL-based
circuit that affects the sampling
behavior and conversion time of
the A/D converter when channel 1
is selected. The PLL pre-trigger
circuit has two modes of opera-
tion; the first mode allows more
precise control of the time at
which the analog input voltage is
effectively sampled, while the
second mode essentially
eliminates the time between when
the external convert start
command is given and when out-
put data is available (reducing it
to less than 1
μ
s). A brief
description of how the A/D con-
verter works with the pre-trigger
circuit disabled will help explain
how the pre-trigger circuit affects
operation when it is enabled.
With the pre-trigger circuit is
disabled (pre-trigger mode 0),
Figure 20 illustrates the relation-
ship between the convert start
command, the weighting function
used to average the modulator
data, and the data ready signal.
The weighted averaging of the
modulator data begins immedi-
ately following the convert start
command. The weighting func-
tion increases for half of the con-
version cycle and then decreases
back to zero, at which time the
data ready signal is given,
completing the conversion cycle.
The analog signal is effectively
sampled at the peak of the
weighting function, half-way
through the conversion cycle.
This is the default mode.
If the convert start signal is
periodic (i.e., at a fixed fre-
quency) and the PLL pre-trigger
circuit is enabled (pre-trigger
modes 1 or 2), either the peak of
the weighting function or the end
of the conversion cycle can be
aligned to the external convert
start command, as shown in
Figure 20. The Digital Interface
IC can therefore synchronize the
conversion cycle so that either
the beginning, the middle, or the
end of the conversion is aligned
with the external convert start
command, depending on whether
pre-trigger mode 0, 1, or 2 is
selected, respectively. The only
requirement is that the convert
start signal for channel 1 be
Figure 20. Pre-Trigger Modes 0, 1, and 2.
periodic. If the signal is not
periodic and pre-trigger mode 1
or 2 is selected, then the pre-
trigger circuit will not function
properly.
An important distinction should
be made concerning the differ-
ence between conversion time
and signal delay. As can be seen
in Figure 20, the amount of time
from the peak of the weighting
function (when the input signal is
being sampled) to when output
data is ready is the same for all
three modes. This is the actual
delay of the analog signal through
the A/D converter and is indepen-
dent of the “conversion time,”
which is simply the time between
the convert start signal and the
data ready signal. Because signal
delay is the true measure of how
much phase shift the A/D
converter adds to the signal, it
should be used when making
calculations of phase margin and
loop stability in feedback
systems.
There are different reasons for
using each of the pre-trigger
modes. If the signal is not
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