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參數(shù)資料
| 型號： | HC4046 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | Phase-Locked Loop |
| 中文描述： | 鎖相環(huán) |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 134K |
| 代理商： | HC4046 |
SL74HC4046
S ystem Logic
Semiconductor
SLS
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
25
°
C
to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
V
IH
Minimum High-Level
Input Voltage DC
Coupled
SIG
IN
, COMP
IN
V
OUT
= 0.1 V or V
CC
-0.1 V
I
OUT
≤
20
μ
A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low -Level
Input Voltage DC
Coupled
SIG
IN
, COMP
IN
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
μ
A
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
OH
Minimum High-Level
Output Voltage
PCP
OUT
, PCn
OUT
V
IN
=V
IH
or V
IL
I
OUT
≤
20
μ
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
IN
= V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum Low-Level
Output Voltage Q
a
-Q
h
PCP
OUT
, PCn
OUT
V
IN
=V
IH
or V
IL
I
OUT
≤
20
μ
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
IN
Maximum Input
Leakage Current
SIG
IN
, COMP
IN
V
IN
=V
CC
or GND
2.0
3.0
4.5
6.0
±
3.0
±
7.0
±
18.0
±
30.0
±
0.5
±
4.0
±
9.0
±
23.0
±
38.0
±
5.0
±
5.0
±
11.0
±
27.0
±
45.0
±
10
μ
A
I
OZ
Maximum Three-State
Leakage Current
PC2
OUT
Output in High-Impedance
State
V
IN
= V
IL
or V
IH
V
OUT
=V
CC
or GND
6.0
μ
A
I
CC
Maximum Quiescent
Supply Current
(per Package)
(VCO disabled)
Pins 3,5 and 14 at V
CC
Pin 9 at GND; Input
Leacage at
Pin 3 and 14 to be
excluded
V
IN
=V
CC
or GND
I
OUT
=0
μ
A
6.0
4.0
40
160
μ
A
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