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參數(shù)資料
| 型號： | HC4053 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | IC-VLTG REG 125V-1A |
| 中文描述： | 模擬多路復(fù)用器/解復(fù)用器 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 87K |
| 代理商： | HC4053 |
SL74HC4053
S ystem Logic
Semiconductor
SLS
Analog Multiplexer/Demultiplexer
High-Performance Silicon-Gate CMOS
The SL74HC4053 utilize silicon-gate CMOS technology to achieve
fast propagation delays, low ON resistances, and low OFF leakage
currents. These analog multiplexers/demultiplexers control analog
voltages that may vary across the complete power supply range (from
V
CC
to V
EE
).
The Channel-Select inputs determine which one of the Analog
Inputs/Outputs is to be connected, by means of an analog switch, to
the Common Output/Input.When the Enable pin is high, all analog
switches are turned off.
The Channel-Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LS/ALSTTL outputs.
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Analog Power Supply Range (V
CC
-V
EE
)=2.0 to 12.0 V
Digital (Control) Power Supply Range (V
CC
-GND)=2.0 to 6.0 V
Low Noise
ORDERING INFORMATION
SL74HC4053N Plastic
SL74HC4053D SOIC
T
A
= -55
°
to 125
°
C for all packages
PIN ASSIGNMENT
FUNCTION TABLE
Control Inputs
ON
Enable
Select
Channels
C
B
A
L
L
L
L
Z0
Y0
X0
L
L
L
H
Z0
Y0
X1
L
L
H
L
Z0
Y1
X0
L
L
H
H
Z0
Y1
X1
L
H
L
L
Z1
Y0
X0
L
H
L
H
Z1
Y0
X1
L
H
H
L
Z1
Y1
X0
L
H
H
H
Z1
Y1
X1
H
X
X
X
None
X = don’t care
LOGIC DIAGRAM
Triple Single-Pole, Double-Position
Plus Common Off
PIN 16 =V
CC
PIN 7 = V
EE
PIN 8 = GND
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