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參數(shù)資料
| 型號： | HC4094 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | T-NPN-SI HIGH VLTG AMP |
| 中文描述： | 8位串行輸入鎖存移位寄存器與三態(tài)輸出（高性能硅柵CMOS） |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 315K |
| 代理商： | HC4094 |
SL74HC4094
S ystem Logic
Semiconductor
SLS
8-Bit Serial-Input Shift Register With Latched
3-State Outputs
High-Performance Silicon-Gate CMOS
The SL74HC4094 is identical in pinout to the LS/ALS4094. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of an 8-bit shift register and 8-bit D-type latch
with three-state parallel outputs. Data is shifted serially through the
shift register on the positive going transition of the clock input signal.
The output of the last stage SQ
H
can be used to cascade several
devices.
Data on the SQ
H
output is transferred to a second output (SQ
H
’) on
the following negative transition of the clock input signal. The data of
each stage of the shift register is provided with a latch, which latches
data on the negative going transition of the Strobe input signal. When
the Strobe input is held high, data propagates through the latch to a 3-
state output buffer.
This buffer is enabled when Output Enable input is taken high.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
μ
A
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC4094N Plastic
SL74HC4094D SOIC
T
A
= -55
°
to 125
°
C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =V
CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Parallel
Outputs
Serial
Outputs
Clock Output
Enable
Strobe A Q
A
Q
N
SQ
H
SQ
H
’
L
X
X
Z
Z
Q6 NC
L
X
X
Z
Z
NC SQ
H
H
L
X NC
NC
Q6 NC
H
H
L
L
Q
N-1
Q6 NC
H
H
H
H
Q
N-1
Q6 NC
H
X
X NC
NC
NC SQ
H
NC = No Change
Z = high impedance
X = don’t care
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