參數(shù)資料
型號(hào): HB52F169EN
廠商: Hitachi,Ltd.
英文描述: 64 MB Unbuffered SDRAM DIMM(64 MB 未緩沖同步DRAM DIMM)
中文描述: 64 MB的無緩沖SDRAM的內(nèi)存(64 MB的未緩沖同步的DRAM內(nèi)存)
文件頁數(shù): 38/71頁
文件大?。?/td> 906K
代理商: HB52F169EN
HB52F88EM-75F, HB52F89EM-75F, HB52F168EN-75F, HB52F169EN-
38
Notes:
1.H: V
IH
. L: V
IL
.
×
: V
IH
or V
IL
.
The other combinations are inhibit.
2.An interval of t
DPL
is required between the final valid data input and the precharge command.
3.If t
RRD
is not satisfied, this operation is illegal.
4.Illegal for same bank, except for another bank.
5.Illegal for all banks.
6.NOP for same bank, except for another bank.
From PRECHARGE state, command operation
To [DESL], [NOP] or [BST]:
When these commands are executed, the SDRAM module enters the IDLE
state after t
RP
has elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [BST], [PRE] or [PALL]:
These commands result in no operation.
To [ACTV]:
The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]:
The SDRAM module enters refresh mode (auto-refresh or self-refresh).
To [MRS]:
The SDRAM module enters the mode register set cycle.
Current state
Write with auto-
precharge
S
H
RE
×
CE
×
W
×
Address
×
Command
DESL
Operation
Continue burst to end and
precharge
Continue burst to end and
precharge
ILLEGAL
ILLEGAL*
4
ILLEGAL*
4
Other bank active
ILLEGAL on same bank*
3
ILLEGAL*
4
ILLEGAL
ILLEGAL
Enter IDLE after t
RC
Enter IDLE after t
RC
Enter IDLE after t
RC
ILLEGAL*
5
ILLEGAL*
5
ILLEGAL*
5
ILLEGAL*
5
ILLEGAL
ILLEGAL
L
H
H
H
×
NOP
L
L
L
L
H
H
H
L
H
L
L
H
L
H
L
H
×
BA, CA, A10 READ/READ A
BA, CA, A10 WRIT/WRIT A
BA, RA
ACTV
BST
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
×
H
H
H
H
L
L
L
L
H
L
L
×
H
H
L
L
H
H
L
L
L
H
L
×
H
L
H
L
H
L
H
L
BA, A10
×
MODE
×
×
×
BA, CA, A10 READ/READ A
BA, CA, A10 WRIT/WRIT A
BA, RA
ACTV
BA, A10
PRE, PALL
×
REF, SELF
MODE
MRS
PRE, PALL
REF, SELF
MRS
DESL
NOP
BST
Refresh (auto-
refresh)
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