參數(shù)資料
型號(hào)： HB52F169EN
廠商： Hitachi,Ltd.
英文描述： 64 MB Unbuffered SDRAM DIMM(64 MB 未緩沖同步DRAM DIMM)
中文描述： 64 MB的無(wú)緩沖SDRAM的內(nèi)存（64 MB的未緩沖同步的DRAM內(nèi)存）
文件頁(yè)數(shù)： 34/71頁(yè)
文件大?。?/td> 906K
代理商： HB52F169EN
HB52F88EM-75F, HB52F89EM-75F, HB52F168EN-75F, HB52F169EN-
34
Row address strobe and bank activate [ACTV]:
This command activates the bank that is selected by bank
select address (BA) and determines the row address (AX0 to AX11). When A12 and A13 are Low, bank 0
is activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High,
bank 2 is activated. When A12 and A13 are High, bank 3 is activated.
Precharge selected bank [PRE]:
This command starts precharge operation for the bank selected by A12/
A13. If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12
is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected.
Precharge all banks [PALL]:
This command starts a precharge operation for all banks.
Refresh [REF/SELF]:
This command starts the refresh operation. There are two types of refresh operation,
the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]:
The SDRAM module has a mode register that defines how it operates. The mode
register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the
mode register configuration. After power on, the contents of the mode register are undefined, execute the
mode register set command to set up the mode register.
DQMB Truth Table
Note: H: V
IH
. L: V
IL
.
×
: V
IH
or V
IL
.
Write: I
DID
is needed.
Read: I
DOD
is needed.
The SDRAM module can mask input/output data by means of DQMB.
During reading, the output buffer is set to Low-Z by setting DQMB to Low, enabling data output. On the
other hand, when DQMB is set to High, the output buffer becomes High-Z, disabling data output.
During writing, data is written by setting DQMB to Low. When DQMB is set to High, the previous data is
held (the new data is not written). Desired data can be masked during burst read or burst write by setting
DQMB. For details, refer to the DQMB control section of the SDRAM module operating instructions.
CKE
n - 1
H
H
Command
Write enable/output enable
Write inhibit/output disable
Symbol
ENB
MASK
n
×
×
DQMB
L
H
相關(guān)PDF資料
PDF描述
HB52F89EM 64 MB Unbuffered SDRAM DIMM(64 MB 未緩沖同步DRAM DIMM)
HB52R1289E22 1 GB Registered SDRAM DIMM 1 GB Registered SDRAM DIMM (36 pcs of 64 M 】 4 Components) PC100 SDRAM
HB52R1289E22-A6B 1 GB Registered SDRAM DIMM 1 GB Registered SDRAM DIMM (36 pcs of 64 M 】 4 Components) PC100 SDRAM
HB52R1289E22-B6B 1 GB Registered SDRAM DIMM 1 GB Registered SDRAM DIMM (36 pcs of 64 M 】 4 Components) PC100 SDRAM
HB52R1289E22 1 GB Registered SDRAM DIMM(1GB 寄存同步DRAM DIMM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HB52F328DC-75B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
HB52F328DC-75BL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
HB52F328EM-75B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB Unbuffered SDRAM DIMM
HB52F329EM-75B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB Unbuffered SDRAM DIMM
HB52F648EN-75B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512 MB Unbuffered SDRAM DIMM, 133 MHz Memory Bus PC133 SDRAM
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