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參數(shù)資料
| 型號： | GS9062-CF |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9062 HD-LINX-TM II SD-SDI and DVB-ASI Serializer |
| 中文描述： | GS9062的HD - LINX進程，商標第二SD - SDI和DVB - ASI在內(nèi)串行器 |
| 文件頁數(shù)： | 24/46頁 |
| 文件大小： | 473K |
| 代理商： | GS9062-CF |
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GS9062 Data Sheet
22209 - 5
May 2005
24 of 46
When DETECT_TRS is HIGH, the flywheel will be locked to the embedded TRS
signals in the parallel input data. Both 8-bit and 10-bit TRS code words will be
identified by the device.
The flywheel 'learns' the video standard by timing the horizontal and vertical
reference information supplied a the H, V, and F input pins, or contained in the TRS
ID words of the received video data. Full synchronization of the flywheel to the
received video standard therefore requires one complete video frame.
Once synchronization has been achieved, the flywheel will continue to monitor the
received TRS timing or the supplied H, V, and F timing information to maintain
synchronization.
3.3.2 HVF Timing Signal Extraction
As discussed above, the GS9062's internal flywheel may be locked to externally
provided H, V, and F signals when DETECT_TRS is set LOW by the application
layer.
The H signal timing should also be configured via the H_CONFIG bit of the internal
IOPROC_DISABLE register as either active line based blanking or TRS based
blanking,
Packet Generation and Insertion on page 28
.
Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this
mode, the H input should be HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words. This is the default H timing assumed by
the device.
When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H
input should be set HIGH for the entire horizontal blanking period as indicated by
the H bit in the associated TRS words.
The timing of these signals is shown in
Figure 3-2
.
Figure 3-2: H, V, F Timing
H:V:F TIMING – 20-BIT INPUT MODE
PCLK
CHROMA DATA OUT
LUMA DATA OUT
H
000
3FF
XYZ
000
V
F
000
3FF
(XYZ
000
H:V:F TIMING – 10-BIT INPUT MODE
MULTIPLEXED
Y/Cr/Cb DATA OUT
PCLK
H
V
F
XYZ
000
000
3FF
XYZ
000
000
3FF
H SIGNAL TIMING:
H_CONFIG = LOW
H_CONFIG = HIGH
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| GS9062-CFE3 | 制造商:Semtech Corporation 功能描述:Dual Standard Serializer 80-Pin LQFP 制造商:Semtech Corporation 功能描述:Transmitter for SD-SDI & DVB-ASI |
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| GS9064ACKDE3 | 制造商:Semtech Corporation 功能描述:Adaptive Cable Equalizer. High-speed BiCMOS integrated circuit. 16-Pin SOIC 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064ACTDE3 | 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
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