參數(shù)資料
型號(hào): GS816118
廠商: Electronic Theatre Controls, Inc.
元件分類: DRAM
英文描述: 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
中文描述: 1M×18,512k×32,512k×36 18M位同步突發(fā)靜態(tài)存儲(chǔ)器
文件頁(yè)數(shù): 29/36頁(yè)
文件大?。?/td> 945K
代理商: GS816118
GS816118(T/D)/GS816132(D)/GS816136(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.13 11/2004
29/36
1999, GSI Technology
JTAG Port Recommended Operating Conditions and DC Characteristics
JTAG Port AC Test Conditions
Parameter
Symbol
V
IHJ3
V
ILJ3
V
IHJ2
V
ILJ2
I
INHJ
I
INLJ
I
OLJ
V
OHJ
V
OLJ
V
OHJC
V
OLJC
Min.
Max.
V
DD3
+0.3
Unit Notes
3.3 V Test Port Input High Voltage
2.0
V
1
3.3 V Test Port Input Low Voltage
0.3
0.8
V
1
2.5 V Test Port Input High Voltage
0.6 * V
DD2
V
DD2
+0.3
0.3 * V
DD2
V
1
2.5 V Test Port Input Low Voltage
0.3
V
1
TMS, TCK and TDI Input Leakage Current
300
1
uA
2
TMS, TCK and TDI Input Leakage Current
1
100
uA
3
TDO Output Leakage Current
1
1
uA
4
Test Port Output High Voltage
1.7
V
5, 6
Test Port Output Low Voltage
0.4
V
5, 7
Test Port Output CMOS High
V
DDQ
– 100 mV
V
5, 8
Test Port Output CMOS Low
100 mV
V
5, 9
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Input Under/overshoot voltage must be
2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
V
ILJ
V
IN
V
DDn
0 V
V
IN
V
ILJn
Output Disable, V
OUT
= 0 to V
DDn
The TDO output driver is served by the V
DDQ
supply.
I
OHJ
=
4 mA
I
OLJ
= + 4 mA
I
OHJC
= –100 uA
I
OHJC
= +100 uA
Notes:
1.
2.
Include scope and jig capacitance.
Test conditions as shown unless otherwise noted.
Parameter
Conditions
V
DD
– 0.2 V
0.2 V
1 V/ns
V
DDQ
/2
V
DDQ
/2
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
DQ
V
DDQ
/2
50
30pF
*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
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