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參數(shù)資料
| 型號(hào)： | GS816118 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| 中文描述： | 1M×18，512k×32，512k×36 18M位同步突發(fā)靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 12/36頁(yè) |
| 文件大?。?/td> | 945K |
| 代理商： | GS816118 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)
GS816118(T/D)/GS816132(D)/GS816136(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.13 11/2004
12/36
1999, GSI Technology
Synchronous Truth Table
Operation
Address Used
State
Diagram
Key
5
X
R
R
W
CR
CR
CW
CW
E
1
ADSP
ADSC
ADV
W
3
DQ
4
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
1.
X = Don’t Care, H = High, L = Low
2.
W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
3.
G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
4.
All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
5.
Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See
BOLD
items above.
6.
Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See
ITALIC
items above.
None
External
External
External
Next
Next
Next
Next
Current
Current
Current
Current
H
L
L
L
X
H
X
H
X
H
X
H
X
L
H
H
H
X
H
X
H
X
H
X
L
X
L
L
H
H
H
H
H
H
H
H
X
X
X
X
L
L
L
L
H
H
H
H
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
Q
Q
D
Q
Q
D
D
Q
Q
D
D
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS816118D | 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| GS816218BGD-150 | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816236BGD-200I | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816236BGD-250 | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816236BGD-250I | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS816118BD-150 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 165FBGA - Trays |
| GS816118BD-150I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 165FBGA - Trays |
| GS816118BD-150IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 18MBIT 1MX18 7.5NS/3.8NS 165FPBGA - Trays |
| GS816118BD-150V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 18MBIT 1MX18 7.5NS/3.8NS 165FPBGA - Trays |
| GS816118BD-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 6.5NS/3NS 165FBGA - Trays |
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