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參數(shù)資料
| 型號(hào)： | GS816118 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| 中文描述： | 1M×18，512k×32，512k×36 18M位同步突發(fā)靜態(tài)存儲(chǔ)器 |
| 文件頁數(shù)： | 1/36頁 |
| 文件大?。?/td> | 945K |
| 代理商： | GS816118 |
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GS816118(T/D)/GS816132(D)/GS816136(T/D)
1M x 18, 512K x 32, 512K x 36
18Mb Sync Burst SRAMs
250 MHz
–
133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 2.13 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/36
1999, GSI Technology
Features
FT pin for user-configurable flow through or pipeline
operation
Single Cycle Deselect (SCD) operation
IEEE 1149.1 JTAG-compatible Boundary Scan
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP and 165-bump BGA
packages
Functional Description
Applications
The GS816118(T/D)/GS816132(D)/GS816136(T/D) is an
18,874,368-bit high performance synchronous SRAM with a 2-bit
burst address counter. Although of a type originally developed for
Level 2 Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs
(ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin (Pin 14). Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the Data
Output Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.
SCD Pipelined Reads
The GS816118(T/D)/GS816132(D)/GS816136(T/D) is a SCD (Single
Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle
Deselect) versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs begin
turning off their outputs immediately after the deselect command has
been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS816118(T/D)/GS816132(D)/GS816136(T/D) operates on a 2.5
V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible.
Separate output power (V
DDQ
) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
2.5
4.0
4.4
5.0
6.0
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x18)
Curr (x36)
2.7
3.0
3.4
3.8
6.7
4.0
7.5
ns
ns
3.3 V
280
330
275
320
255
300
250
295
230
270
230
265
200
230
195
225
185
215
180
210
165
190
165
185
mA
mA
mA
mA
2.5 V
Flow
Through
2-1-1-1
t
KQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
3.3 V
Curr (x18)
Curr (x36)
Curr (x18)
Curr (x36)
175
200
175
200
165
190
165
190
160
180
160
180
150
170
150
170
145
165
145
165
135
150
135
150
mA
mA
mA
mA
2.5 V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS816118D | 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| GS816218BGD-150 | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816236BGD-200I | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816236BGD-250 | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816236BGD-250I | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS816118BD-150 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 165FBGA - Trays |
| GS816118BD-150I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 165FBGA - Trays |
| GS816118BD-150IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 18MBIT 1MX18 7.5NS/3.8NS 165FPBGA - Trays |
| GS816118BD-150V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 18MBIT 1MX18 7.5NS/3.8NS 165FPBGA - Trays |
| GS816118BD-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 6.5NS/3NS 165FBGA - Trays |
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