參數(shù)資料
型號(hào)： GS816118
廠商： GSI TECHNOLOGY
英文描述： 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水線(xiàn)式和流通型同步NBT靜態(tài)RAM)
中文描述： 16Mb的流水線(xiàn)和流量，通過(guò)同步唑的SRAM（1,600位流水線(xiàn)式和流通型同步唑靜態(tài)內(nèi)存）
文件頁(yè)數(shù)： 24/32頁(yè)
文件大小： 584K
代理商： GS816118
Rev: 2.07 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
24/32
1999, Giga Semiconductor, Inc.
Preliminary
GS816118/36T-225/200/180/166/150/133
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1
compliant because some of the mandatory instructions are uniquely implemented. The TAP on this device may be used to monitor
all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This
device will not perform INTEST or the preload portion of the SAMPLE / PRELOAD command.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
P
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
1
1
0
0
10 9 8 7 6 5 4 3 2 1
0
x36
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0 0 1 1 0 1 1 0 0 1
0 0 1 1 0 1 1 0 0 1
1
1
x18
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
· · ·
· · ·
n
0
1
2
0
1
2
· · ·
0
1
2
· · ·
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
相關(guān)PDF資料
PDF描述
GS8161E18BD-200I 1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGD-200I 1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGD-250 1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS816118BD-150 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 165FBGA - Trays
GS816118BD-150I 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 165FBGA - Trays
GS816118BD-150IV 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 18MBIT 1MX18 7.5NS/3.8NS 165FPBGA - Trays
GS816118BD-150V 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 18MBIT 1MX18 7.5NS/3.8NS 165FPBGA - Trays
GS816118BD-200 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 6.5NS/3NS 165FBGA - Trays
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