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參數(shù)資料
| 型號： | GS4915 |
| 廠商： | Gennum Corporation |
| 英文描述： | CONN,S/R,8 POS,254C-08-1, CLOSED END STRAIN RELIEF COVER |
| 中文描述： | ClockCleaner⑩ |
| 文件頁數(shù)： | 6/26頁 |
| 文件大小： | 533K |
| 代理商： | GS4915 |
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GS4915 Data Sheet
39145 - 3
November 2007
6 of 26
18
DOUBLE
Non
synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS compatible.
Controls the output frequency of the cleaned clock, for HD input clocks.
See
Section 3.5
for operation.
19
SKEW_EN
Non
synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS compatible.
Selects the phase of the output clock with respect to the selected input
clock.
See
Section 3.6
for operation.
21
LOCK
Non
synchronous
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS compatible.
This pin will be HIGH when the output clock is locked to the selected input
clock.
It will be LOW otherwise.
23
SE_VDD
–
Power
Positive power supply connection for the single-ended clock driver.
Determines the output level of CLKOUT_SE. Connect to filtered +1.8V DC
or +3.3V DC.
NOTE: If the single-ended clock output is not used, this pin should be tied
to ground.
24
CLKOUT_SE
–
Output
CLOCK SIGNAL OUTPUT
Signal levels are LVCMOS compatible.
Single-ended video clock output signal.
See
Section 3.7.2
for operation.
25
D_VDD
–
Power
Positive power supply connection for the single-ended output clock buffer.
Connect to filtered +1.8V DC.
NOTE: If the single-ended clock output is not used, this pin should be tied
to ground.
27
DIFF_OUT_VDD
–
Power
Positive power supply connection for the LVDS clock outputs. Connect to
filtered +1.8V DC.
NOTE: If the LVDS clock outputs are not used, this pin should be tied to
ground.
29, 28
CLKOUT,
CLKOUT
–
Output
CLOCK SIGNAL OUTPUT
Differential video clock output signal.
This is the lowest jitter output of the device.
See
Section 3.7.1
for operation.
32
DIV_VDD
–
Power
Positive power supply connection for the divider block. Connect to filtered
+1.8V DC.
33,34
VCO, VCO
Analog
Input
Differential input for the external VCO reference signal. When using the
recommended VCO, leave VCO unconnected.
See
Section 3.3.4
for operation.
35
VCO_GND
–
Power
Ground reference for the external voltage controlled oscillator. Connect to
pins 2, 4, 6, and 8 of the GO1555.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS6332 | 3 Pin, Low-Power, P Reset Circuits |
| GS6332UR15D1 | 3 Pin, Low-Power, P Reset Circuits |
| GS6333UR19D1 | FC/ACP F.O. SINGLE MODE IN-LINE ATTENUATOR 10DB |
| GS6332UR19D1 | FC/PC F.O. SINGLE MODE IN-LINE ATTENUATOR 5 DB |
| GS6333UR23D1 | DEU9PTIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4915_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
| GS4915-CNE3 | 制造商:Semtech Corporation 功能描述:QFN-40 pin (490/tray) |
| GS4915INE3 | 制造商:Gennum Corporation 功能描述:CLOCKCLEANER HD/SD VIDEO INPUT 40QFN 制造商:Gennum Corporation 功能描述:CLOCKCLEANER, HD/SD, VIDEO INPUT, 40QFN |
| GS4915-INE3 | 功能描述:IC CLK JITTER CLEANR 40QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:ClockCleaner™ 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| GS4953 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:臺灣晶群科技 |
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