參數(shù)資料
型號: GS4915
廠商: Gennum Corporation
英文描述: CONN,S/R,8 POS,254C-08-1, CLOSED END STRAIN RELIEF COVER
中文描述: ClockCleaner⑩
文件頁數(shù): 18/26頁
文件大?。?/td> 533K
代理商: GS4915
GS4915 Data Sheet
39145 - 3
November 2007
18 of 26
3.5 Output Clock Frequency and Jitter
The frequency and jitter of the output clock are determined by:
the frequency of the input clock,
the differential or single-ended input and output clocks,
the selected frequency mode,
the selected bypass mode, and
the setting of the DOUBLE pin.
When the DOUBLE pin is set HIGH, the output clock frequency will be double the
input only when the selected input clock frequency is determined to be 74.25MHz
± 0.4%. Otherwise, the setting of the DOUBLE pin will have no effect on the
frequency of the output clock.
The output clock will be low jitter when the LOCK pin is HIGH. The only exception
to this is if operating in Manual Bypass mode, see
Section 3.4.2
.
Table 3-4
,
Table 3-5
, and
Table 3-6
summarize the output frequency and LOCK behaviour of
the device given the frequency of the input clock, the selected frequency mode,
and the setting of the DOUBLE pin for Autobypass, Manual Bypass, and Forced
Output modes, respectively. In each table, 'X' indicates a "don't care" condition.
Table 3-4: Output Behaviour in Autobypass Mode
FCTRL[1:0]
Input
DOUBLE
LOCK
Output
Auto [00]
27MHz
X
HIGH
27MHz
74.25MHz
0
HIGH
74.25MHz
1
HIGH
148.5MHz
148.5MHz
X
HIGH
148.5MHz
Other
X
LOW
Input
Fixed – 27MHz
[01]
27MHz
X
HIGH
27MHz
74.25MHz
X
LOW
74.25MHz
148.5MHz
X
LOW
148.5MHz
Other
X
LOW
Input
Fixed –
74.25MHz [10]
27MHz
X
LOW
27MHz
74.25MHz
0
HIGH
74.25MHz
1
HIGH
148.5MHz
148.5MHz
X
LOW
148.5MHz
Other
X
LOW
Input
Fixed –
148.5MHz [11]
27MHz
X
LOW
27MHz
74.25MHz
X
LOW
74.25MHz
148.5MHz
X
HIGH
148.5MHz
Other
X
LOW
Input
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