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參數(shù)資料
| 型號： | GS4915 |
| 廠商： | Gennum Corporation |
| 英文描述： | CONN,S/R,8 POS,254C-08-1, CLOSED END STRAIN RELIEF COVER |
| 中文描述： | ClockCleaner⑩ |
| 文件頁數(shù)： | 14/26頁 |
| 文件大小： | 533K |
| 代理商： | GS4915 |
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GS4915 Data Sheet
39145 - 3
November 2007
14 of 26
3.3.1 Phase Detector
The GS4915's phase detector can identify phase misalignment between the
selected input clock and the reference clock provided by the external VCO, and
correspondingly signal the charge pump to alter the VCO control voltage.
3.3.2 Charge Pump
The charge pump block of the PLL is powered externally by +2.5V DC applied to
CP_VDD. This is provided by the GS4915 itself at the VCO_VDD pin. An external
RC filter at the CP_VDD pin is recommended to reduce supply noise for best jitter
performance. Please refer to the
Typical Application Circuit on page 22
.
An external resistance connected to the CP_RES pin is used to set the charge
pump reference current of the device. Typically, the CP_RES pin will be connected
through 10k
Ω
to VCO_GND.
3.3.3 Loop Filter
The GS4915 PLL loop filter is an external first order filter formed by a series RC
connection as shown in
Table 3-1: Loop Filter Component Values
. The loop filter
resistor value sets the bandwidth of the PLL and the capacitor value controls its
stability and lock time. A loop filter resistor value between 1
Ω
and 20
Ω
and a loop
filter capacitor value between 1μF and 33μF are recommended.
The GS4915 uses a non-linear, bang-bang, PLL, therefore its bandwidth scales
linearly with the input jitter amplitude - greater input jitter results in a smaller loop
bandwidth causing more of the input jitter to be rejected. For a given input jitter
amplitude, a smaller loop filter resistor produces a narrower loop bandwidth. With
an input jitter amplitude of 300ps, for example, the PLL bandwidth can be adjusted
from 2KHz to 40KHz by varying the loop filter resistor, as shown in the table below.
For use with GS4911, a narrow loop bandwidth is recommended.
Increasing the loop filter capacitor value increases the stability of the PLL, but
results in a longer lock time. For loop filter resistors smaller than 7
Ω
, a capacitor
value of 33μF is recommended, while larger resistor values can accommodate
smaller capacitors. Sample combinations of the loop filter resistor and capacitor
values are shown in the table below, along with the resulting loop bandwidth.
Additional loop bandwidths can be achieved by using different loop filter resistor
values.
Table 3-1: Loop Filter Component Values
Loop Filter
R
Typical Loop
Bandwidth*
Recommended
Loop Filter C
Comments
1
Ω
2kHz
33
μ
F
Narrow bandwidth - provides maximum jitter reduction. Long lock-time.
7
Ω
8kHz
10
μ
F
20
Ω
40kHz
1
μ
F
Wide bandwidth. Fast lock-time.
Note:
1. *Measured with 300ps pk-pk input jitter on CLK.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4915_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
| GS4915-CNE3 | 制造商:Semtech Corporation 功能描述:QFN-40 pin (490/tray) |
| GS4915INE3 | 制造商:Gennum Corporation 功能描述:CLOCKCLEANER HD/SD VIDEO INPUT 40QFN 制造商:Gennum Corporation 功能描述:CLOCKCLEANER, HD/SD, VIDEO INPUT, 40QFN |
| GS4915-INE3 | 功能描述:IC CLK JITTER CLEANR 40QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:ClockCleaner™ 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| GS4953 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:臺灣晶群科技 |
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