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參數(shù)資料
| 型號： | GS4915 |
| 廠商： | Gennum Corporation |
| 英文描述： | CONN,S/R,8 POS,254C-08-1, CLOSED END STRAIN RELIEF COVER |
| 中文描述： | ClockCleaner⑩ |
| 文件頁數(shù)： | 21/26頁 |
| 文件大?。?/td> | 533K |
| 代理商： | GS4915 |
GS4915 Data Sheet
39145 - 3
November 2007
21 of 26
3.7 Clock Outputs
The GS4915 presents both differential and single-ended clock outputs. When the
LOCK output signal is HIGH, these clock outputs will be low-jitter and locked to the
selected input clock.
NOTE: If in Manual Bypass mode, the LOCK pin may be HIGH although the output
clock will always be a copy of the input clock, and NOT the cleaned clock.
The frequency of the differential and single-ended clock outputs will be identical
and will be determined as described in
Section 3.5
.
3.7.1 Differential Clock Output
A CML-based driver is used to provide the differential clock output at the CLKOUT
and CLKOUT pins. Although this driver will output a signal amplitude that is
compatible to the TIA/EIA-644 LVDS standard, it has an incompatible common
mode level. Therefore, AC-coupling and external biasing resistors are required if
interfacing the differential clock outputs from the GS4915 to a true LVDS receiver.
The common mode is, however, compatible with the LVDS inputs on most FPGAs
and can be DC coupled.
This is the lowest-jitter output of the GS4915.
The differential clock output driver uses a separate power supply of +1.8V DC
supplied via the DIFF_OUT_VDD pin.
3.7.2 Single-Ended Clock Output
The single-ended output clock is present at the CLKOUT_SE pin. The signal will
operate at either 1.8V or 3.3V CMOS levels, as determined by the voltage applied
to the D_VDD pin.
The single-ended clock output pre-drive uses a separate power supply of +1.8V
DC supplied via the SE_VDD pin.
3.8 Device Reset
3.8.1 Hardware Reset
In order to reset the GS4915 to their defaults conditions, the RESET pin must be
held LOW for a minimum of t
reset
= 0.5ms.
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| GS6332 | 3 Pin, Low-Power, P Reset Circuits |
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| GS6333UR19D1 | FC/ACP F.O. SINGLE MODE IN-LINE ATTENUATOR 10DB |
| GS6332UR19D1 | FC/PC F.O. SINGLE MODE IN-LINE ATTENUATOR 5 DB |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4915_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
| GS4915-CNE3 | 制造商:Semtech Corporation 功能描述:QFN-40 pin (490/tray) |
| GS4915INE3 | 制造商:Gennum Corporation 功能描述:CLOCKCLEANER HD/SD VIDEO INPUT 40QFN 制造商:Gennum Corporation 功能描述:CLOCKCLEANER, HD/SD, VIDEO INPUT, 40QFN |
| GS4915-INE3 | 功能描述:IC CLK JITTER CLEANR 40QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:ClockCleaner™ 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| GS4953 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:臺灣晶群科技 |
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