參數(shù)資料
型號(hào): GS4901B
廠商: Gennum Corporation
英文描述: SD Clock and Timing Generator with GENLOCK
中文描述: 統(tǒng)計(jì)時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù): 74/95頁(yè)
文件大?。?/td> 898K
代理商: GS4901B
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
74 of 95
PCLK3_Phase/Divide
2Eh
15-6
Reserved. Set these bits to zero when writing to 2Eh.
2Eh
5-2
PCLK3_Phase - adjusts the output phase of the
PCLK3/PCLK3 clock with respect to the timing output
pins. Phase is delayed in 700ps (nominal) increments
as shown in
Table 3-6
.
Reference:
Section 3.7.1 on page 52
R/W
0
2Eh
1
Divide_By_4 - set this bit HIGH to divide the output
PCLK3/PCLK3 by four.
Setting this bit and bit 0 simultaneously HIGH will give
the full rate video clock on the PCLK3 / PCLK3 pins.
Reference:
Section 3.7.1 on page 52
R/W
0
2Eh
0
Divide_By_2 - set this bit HIGH to divide the output
PCLK3/PCLK3 by two.
Setting this bit and bit 1 simultaneously HIGH will give
the full rate video clock on the PCLK3 / PCLK3 pins.
Reference:
Section 3.7.1 on page 52
R/W
0
PCLK3_Tristate
2Fh
15-2
Reserved. Set these bits to zero when writing to 2Fh.
2Fh
1-0
Set these bits to 11b to tristate the PCLK3 / PCLK3 pins.
Reference:
Section 3.7.1 on page 52
R/W
00b
RSVD
2Fh - 30h
Reserved.
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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