參數(shù)資料
型號(hào)： GS4901B
廠商： Gennum Corporation
英文描述： SD Clock and Timing Generator with GENLOCK
中文描述： 統(tǒng)計(jì)時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁數(shù)： 18/95頁
文件大?。?/td> 898K
代理商： GS4901B
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
18 of 95
58
SDIN_TDI
Synchronous
with
SCLK_TCLK
Input
SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Input / Test Data Input.
Host Mode (JTAG/HOST = LOW):
SDIN_TDI operates as the host interface serial input, SDIN, used to write
address and configuration information to the internal registers of the
device.
JTAG Test Mode (JTAG/HOST = HIGH):
SDIN_TDI operates as the JTAG test data input, TDI.
59
SDOUT_TDO
Synchronous
with
SCLK_TCLK
Output
SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Output / Test Data Output.
Host Mode (JTAG/HOST = LOW):
SDOUT_TDO operates as the host interface serial output, SDOUT, used
to read status and configuration information from the internal registers of
the device.
JTAG Test Mode (JTAG/HOST = HIGH):
SDOUT_TDO operates as the JTAG test data output, TDO.
60
CS_TMS
Synchronous
with
SCLK_TCLK
Input
SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Chip Select / Test Mode Select.
Host Mode (JTAG/HOST = LOW):
CS_TMS operates as the host interface chip select, CS, and is active
LOW.
JTAG Test Mode (JTAG/HOST = HIGH):
CS_TMS operates as the JTAG test mode select, TMS, and is active
HIGH.
61
RESET
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to their default settings or
to reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW):
When asserted LOW, all host registers and functional blocks will be set
to their default conditions. All input and output signals will become high
impedance, except PCLK1 and PCLK2, which will be set LOW.
When set HIGH, normal operation of the device will resume.
The user must hold this pin LOW during power-up and for a minimum of
500 uS after the last supply has reached its operating voltage.
JTAG Test Mode (JTAG/HOST = HIGH):
When asserted LOW, all host registers and functional blocks will be set
to their default conditions and the JTAG test sequence will be held in
reset.
When set HIGH, normal operation of the JTAG test sequence will
resume.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS4901B_09 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK
GS4901BCNE3 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
GS4910B 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK
GS4910BCNE3 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
GS4911ACNE3 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
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