- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384345 > GS4901B (Gennum Corporation) SD Clock and Timing Generator with GENLOCK PDF資料下載
參數(shù)資料
| 型號(hào)： | GS4901B |
| 廠商： | Gennum Corporation |
| 英文描述： | SD Clock and Timing Generator with GENLOCK |
| 中文描述： | 統(tǒng)計(jì)時(shí)鐘和定時(shí)發(fā)生器鎖相 |
| 文件頁數(shù)： | 36/95頁 |
| 文件大?。?/td> | 898K |
| 代理商： | GS4901B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當(dāng)前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
36 of 95
V_Offset (1Ch) - the difference between the reference VSYNC signal and the
output V Sync and/or V Blanking in lines, with a control range of zero to +1
frame. All line-based timing output signals will be delayed by the vertical offset
programmed in this register.
The encoding scheme for the Clock_Phase_Offset register (1Dh) is shown in
Table 3-1
. The offset programmed will be in the positive direction. Note that the
step size will depend on the frequency of the output video clock.
The value programmed in the H_Offset register (1Bh) must not exceed the
maximum number of clock periods per line of the outgoing video standard.
Similarly, the value programmed in the V_Offset register (1Ch) must not exceed
the maximum number of lines per frame of the outgoing standard. Both horizontal
and vertical offsets will be in the positive direction. Negative offsets (advances) are
achieved by programming a value in the appropriate register equal to the maximum
allowable offset minus the desired advance.
NOTES:
1. The device will delay all output timing signals by 2 PCLKs relative to the input
HSYNC reference. This will occur even when the H_Offset register is not
programmed. The user may compensate for this delay by subtracting 2 PCLK
cycles from the desired horizontal offset before loading the value into the host
interface.
2. For both sync and blanking-based input references, the device will advance all
line-based output timing signals by 1 line relative to the input VSYNC
reference for all output standards except VID_STD[5:0] = 4, 6, and 8. This will
occur even when the V_Offset register is not programmed. The user may
compensate for this advance by adding 1 line to the desired vertical offset
before loading this value into the register.
Table 3-1: Clock_Phase_Offset[15:0] Encoding Scheme
VID_STD[5:0]
Setting
Output Video Clock
Frequency
Step Size
(Fraction
of a
PCLK)
Maximum
Number of
Steps
Bits Required to
Set the Number
of Steps
Clock_Phase_Offset
[15:0] Settings
1
f
PCLK
< 20MHz
511
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
b
8
000001b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
3-6
20MHz < f
PCLK
< 40MHz
255
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
b
7
000010b
7
b
6
b
5
b
4
0b
3
b
2
b
1
b
0
7-10
40MHz < f
PCLK
< 54MHz
127
b
6
b
5
b
4
b
3
b
2
b
1
b
0
b
6
000100b
6
b
5
b
4
00b
3
b
2
b
1
b
0
Note: Program Clock_Phase_Offset = 0000 0000 0000 0000b to achieve a zero clock phase offset.
512
---1
256
---1
128
---1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS4901BCNE3 | SD Clock and Timing Generator with GENLOCK |
| GS4910B | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4910BCNE3 | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911B | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911BCNE3 | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4901B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK |
| GS4901BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4910B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4910BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4911ACNE3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。