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參數(shù)資料
| 型號： | GS4901B |
| 廠商： | Gennum Corporation |
| 英文描述： | SD Clock and Timing Generator with GENLOCK |
| 中文描述： | 統(tǒng)計時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 73/95頁 |
| 文件大?。?/td> | 898K |
| 代理商： | GS4901B |
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GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
73 of 95
PCLK1_Phase/Divide
2Ch
15-7
Reserved. Set these bits to zero when writing to 2Ch.
–
–
2Ch
6
Current_P1 - selects the current drive capability of the
PCLK1 pin. Set this bit HIGH for high current drive.
Otherwise, the current drive will be low.
Reference:
Section 3.7.1 on page 52
R/W
0
2Ch
5-2
PCLK1_Phase - adjusts the output phase of the PCLK1
clock with respect to the timing output pins. Phase is
delayed in 700ps (nominal) increments as shown in
Table 3-6
.
Reference:
Section 3.7.1 on page 52
R/W
0
2Ch
1
Divide_By_4 - set this bit HIGH to divide the output
PCLK1 by four.
NOTE: Setting this bit and bit 0 simultaneously HIGH
will hold the PCLK1 pin LOW.
Reference:
Section 3.7.1 on page 52
R/W
0
2Ch
0
Divide_By_2 - set this bit HIGH to divide the output
PCLK1 by two.
NOTE: Setting this bit and bit 1 simultaneously HIGH
will hold the PCLK1 pin LOW.
Reference:
Section 3.7.1 on page 52
R/W
0
PCLK2_Phase/Divide
2Dh
15-7
Reserved. Set these bits to zero when writing to 2Dh.
–
–
2Dh
6
Current_P2 - selects the current drive capability of the
PCLK2 pin. Set this bit HIGH for high current drive.
Otherwise, the current drive will be low.
Reference:
Section 3.7.1 on page 52
R/W
0
2Dh
5-2
PCLK2_Phase - adjusts the output phase of the PCLK2
clock with respect to the timing output pins. Phase is
delayed in 700ps (nominal) increments as shown in
Table 3-6
.
Reference:
Section 3.7.1 on page 52
R/W
0
2Dh
1
Divide_By_4 - set this bit HIGH to divide the output
PCLK2 by four.
NOTE: Setting this bit and bit 0 simultaneously HIGH
will hold the PCLK2 pin LOW.
Reference:
Section 3.7.1 on page 52
R/W
0
2Dh
0
Divide_By_2 - set this bit HIGH to divide the output
PCLK2 by two.
NOTE: Setting this bit and bit 1 simultaneously HIGH
will hold the PCLK2 pin LOW.
Reference:
Section 3.7.1 on page 52
R/W
0
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS4901BCNE3 | SD Clock and Timing Generator with GENLOCK |
| GS4910B | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4910BCNE3 | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911B | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911BCNE3 | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4901B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK |
| GS4901BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4910B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4910BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4911ACNE3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
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