參數(shù)資料
型號: GS1560ACF
廠商: Gennum Corporation
英文描述: GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer
中文描述: GS1560A/GS1561的HD - LINX進程- R的第二雙率解串器
文件頁數(shù): 43/80頁
文件大?。?/td> 842K
代理商: GS1560ACF
GS1560A/GS1561 Data Sheet
27360 - 8
September 2005
43 of 80
3.7.4 HVF Timing Signal Generation
The GS1560A/GS1561 extracts critical timing parameters from either the received
TRS signals (FW_EN/DIS = LOW), or from the internal flywheel-timing generator
(FW_EN/DIS = HIGH).
Horizontal blanking period (H), vertical blanking period (V), and even / odd field (F)
timing are all extracted and presented to the application layer via the H:V:F status
output pins.
The H signal timing is configurable via the H_CONFIG bit of the internal
IOPROC_DISABLE register as either active line based blanking, or TRS based
blanking, (see
Error Correction and Insertion on page 61
).
Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this
mode, the H output is HIGH for the entire horizontal blanking period, including the
EAV and SAV TRS words. This is the default H timing used by the device.
When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H
output will be HIGH for the entire horizontal blanking period as indicated by the H
bit in the received TRS ID words.
The timing of these signals is shown in
Figure 3-3
.
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