參數(shù)資料
型號： GS1559-CB
廠商： Gennum Corporation
英文描述： GS1559 HD-LINX-TM II Multi-Rate Deserializer with Loop-Through Cable Driver
中文描述： GS1559的HD - LINX進程，商標(biāo)第二多速率解串器與環(huán)通電纜驅(qū)動器
文件頁數(shù)： 12/74頁
文件大?。?/td> 686K
代理商： GS1559-CB
GS1559 Data Sheet
30572 - 4
July 2005
12 of 74
G4
IOPROC_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable I/O processing features.
When set HIGH, the following I/O processing features of the device are
enabled:
EDH CRC Error Correction (SD-only)
ANC Data Checksum Correction
Line-based CRC Error Correction (HD-only)
Line Number Error Correction (HD-only)
TRS Error Correction
Illegal Code Remapping
To enable a subset of these features, keep IOPROC_EN/DIS HIGH and
disable the individual feature(s) in the IOPROC_DISABLE register
accessible via the host interface.
When set LOW, the I/O processing features of the device are disabled,
regardless of whether the features are enabled in the IOPROC_DISABLE
register.
G5
SMPTE_BYPASS
Non
Synchronous
Input /
Output
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in slave mode, and will
be an output set by the device in master mode.
Master Mode (MASTER/SLAVE = HIGH)
The SMPTE_BYPASS signal will be HIGH only when the device has
locked to a SMPTE compliant data stream. It will be LOW otherwise.
Slave Mode (MASTER/SLAVE = LOW)
When set HIGH in conjunction with DVB_ASI = LOW, the device will be
configured to operate in SMPTE mode. All I/O processing features may be
enabled in this mode.
When set LOW, the device will not support the descrambling, decoding or
word alignment of received SMPTE data. No I/O processing features will
be available.
G6
RESET_TRST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings and to
reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW)
When asserted LOW, all functional blocks will be set to default conditions
and all input and output signals become high
impedance, including the
serial digital outputs SDO and
SDO.
Must be set HIGH for normal device operation.
NOTE: When in slave mode, reset the device after the SD/
HD
input has
been initially configured, and after each subsequent SD/HD data rate
change.
JTAG Test Mode (JTAG/HOST = HIGH)
When asserted LOW, all functional blocks will be set to default and the
JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence resumes.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料
PDF描述
GS1559-CBE2 GS1559 HD-LINX-TM II Multi-Rate Deserializer with Loop-Through Cable Driver
GS2905 500mA CMOS LDO Voltage Regulator
GS2905X15 500mA CMOS LDO Voltage Regulator
GS2905X18 500mA CMOS LDO Voltage Regulator
GS2905X25 500mA CMOS LDO Voltage Regulator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS1559CBE2 制造商:Gennum Corporation 功能描述:DESERIALISER HD/SDI/ASI W/DRV 100BGA 制造商:Gennum Corporation 功能描述:DESERIALISER, HD/SDI/ASI, W/DRV, 100BGA
GS1559-CBE2 功能描述:RF, RFID, WIRELESS RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件
GS1560 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Voltage Controlled Oscillator
GS1560A 制造商:Gennum Corporation 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*