參數(shù)資料
型號(hào)： GMS87C7216Q
廠商： Electronic Theatre Controls, Inc.
元件分類： 8位微控制器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁(yè)數(shù)： 81/121頁(yè)
文件大?。?/td> 1645K
代理商： GMS87C7216Q
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GMS81C7208/7216
FEB. 2005 Ver 1.04
77
20.2 STOP Mode
For applications where power consumption is a critical
factor, device provides reduced power of STOP.
Start the Stop Operation
An instruction that STOP causes to be the last instruction
is executed before going into the STOP mode. In the Stop
mode, the on-chip main-frequency oscillator is stopped.
With the clock frozen, all functions are stopped, but the on-
chip RAM and Control registers are held. The port pins
output the values held by their respective port data register,
the port direction registers. The status of peripherals during
Stop mode is shown below.
Note:
Since the X
IN
pin is connected internally to GND to
avoid current leakage due to the crystal oscillator in STOP
mode, do not use STOP instruction when an external clock
is used as the main system clock.
In the Stop mode of operation, V
DD
can be reduced to minimize
power consumption. Be careful, however, that V
DD
is not re-
duced before the Stop mode is invoked, and that V
DD
is restored
to its normal operating level before the Stop mode is terminated.
The reset should not be activated before V
DD
is restored to its
normal operating level, and must be held active long enough to
allow the oscillator to restart and stabilize.
And after STOP instruction, at least two or more NOP instruction
should be written as shown in example below.
Example)
LDM
LDM
STOP
NOP
NOP
CKCTLR,#0EBH;32.8ms
CKCTLR,#0FBH ;65.5ms
;
:
The interval timer register CKCTLR should be initialized (0F
H
or
0E
H
) by software in order that oscillation stabilization time
should be longer than 20ms before STOP mode.
Release the STOP Mode
The exit from STOP mode is using hardware reset or external in-
terrupt, watch timer, key scan or Timer/Counter.
To release STOP mode, corresponding interrupt should be
enabled before STOP mode.
Specially as a clock source of Timer/Event Counter, EC0 or EC2
pin can release it by Timer/Event Counter
interrupt request
.
Reset redefines all the control registers but does not change the
on-chip RAM. External interrupts allow both on-chip RAM and
Control registers to retain their values.
Start-up is performed to acquire the time for stabilizing oscilla-
tion. During the start-up, the internal operations are all stopped.
Peripheral
STOP Mode
SLEEP Mode
CPU
All CPU operations are disabled
All CPU operations are disabled
RAM
Retain
Retain
LCD Driver
LCD driver operates continuously
LCD driver operates continuously
Basic Interval Timer
Halted
BIT operates continuously
Timer/Event Counter
Halted (Only when the Event counter mode
is enabled, Timer operates normally)
Timer/Event Counter operates continuously
Watch Timer
Watch Timer operates continuously
Watch Timer operates continuously
Main-oscillation
Stop (X
IN
pin = “L”, X
OUT
pin = ”L”)
Oscillation
Oscillation
Sub-oscillation
Oscillation
I/O Ports
Retain
Retain
Control Registers
Retain
Retain
Release Method
RESET, SIO interrupt, Watch Timer inter-
rupt, Timer interrupt (EC0,2), External inter-
rupt
RESET, All interrupts
Table 20-1 Peripheral Operation During Power Down Mode
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