參數(shù)資料
型號(hào)： GMS87C7216Q
廠商： Electronic Theatre Controls, Inc.
元件分類： 8位微控制器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁數(shù)： 64/121頁
文件大小： 1645K
代理商： GMS87C7216Q
GMS81C7208/7216
60
FEB. 2005 Ver 1.04
.
Figure 17-2 Block Diagram of Interrupt
Figure 17-3 Interrupt Enable Flag
INT1
INT0
INT2
INT2IF
IENL
Interrupt Enable
Register (Lower byte)
Interrupt Enable
Register (Higher byte)
IRQL [0DC
H
]
IRQH [0DD
H
]
Interrupt
Vector
Address
Generator
Internal bus line
Internal bus line
Release STOP
To CPU
Interrupt Master
Enable Flag
I-flag
IENH
P
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
[0DA
H
]
[0DB
H
]
INT0IF
INT1IF
T3IF
T2IF
Timer 3
Timer 2
A/D Converter
ADIF
SIOIF
BITIF
Watchdog Timer
BIT
WDTIF
CommuniSerial
Watch Timer
WTIF
T1IF
T0IF
Timer 1
Timer 0
SIOE
INT2E
Timer/Counter 3 Interrupt Enable Flag
Timer/Counter 2 Interrupt Enable Flag
Watch Timer Interrupt Enable Flag
A/D Converter Interrupt Enable Flag
INITIAL VALUE: 0--0 0000
B
ADDRESS: 0DA
H
IENL
-
MSB
LSB
T2E
T3E
ADE
WTE
-
R/W
R/W
Serial Communication Interrupt Enable Flag
External Interrupt 2 Enable Flag
INITIAL VALUE: -000 0000
B
ADDRESS: 0DB
H
IENH
MSB
LSB
R/W
R/W
R/W
-
R/W
Basic Interval Timer Interrupt Enable Flag
Watchdog Timer Interrupt Enable Flag
0: Disable
1: Enable
VALUE
WDTE
R/W
-
T0E
T1E
INT0E
INT1E
BITE
R/W
R/W
R/W
R/W
-
R/W
R/W
-
Timer/Counter 1 Interrupt Enable Flag
Timer/Counter 0 Interrupt Enable Flag
External Interrupt 1 Enable Flag
External Interrupt 0 Enable Flag
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