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| 型號(hào)： | GMS87C7216Q |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類(lèi)： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁(yè)數(shù)： | 67/121頁(yè) |
| 文件大小： | 1645K |
| 代理商： | GMS87C7216Q |
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GMS81C7208/7216
FEB. 2005 Ver 1.04
63
17.4 External Interrupt
The external interrupt on INT0, INT1 and INT3 pins are edge
triggered depending on the edge selection register IEDS (address
0D8
H
) as shown in Figure 17-7.
The edge detection of external interrupt has three transition acti-
vated mode: rising edge, falling edge, and both edge.
Figure 17-7 External Interrupt Block Diagram
INT0 ~ INT2 are multiplexed with general I/O ports (R00~R02).
To use as an external interrupt pin, the bit of Port Mode Register
PMR should be set to “1” correspondingly as shown in Figure 17-
9.
Example:
To use as an INT0 and INT2
:
:
;
**** Set port as an input port R00,R02
LDM
;
;
**** Set port as an external interrupt port
LDM
PMR,#05H
;
;
**** Set Falling-edge Detection
LDM
IEDS,#0001_0001B
:
:
R0DD,#1111_1010B
Response Time
The INT0 ~ INT2 edge are latched into INT1IF ~ INT2IF at every
machine cycle. The values are not actually polled by the circuitry
until the next machine cycle. If a request is active and conditions
are right for it to be acknowledged, a hardware subroutine call to
the requested service routine will be the next instruction to be ex-
ecuted. The DIV itself takes twelve cycles. Thus, a minimum of
twelve complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution of the
first instruction of the service routine.
Figure 17-8 shows interrupt response timings.
Figure 17-8 Interrupt Response Timing Diagram
INT0IF
INT0 pin
INT0 INTERRUPT
INT1IF
INT1 pin
INT1 INTERRUPT
INT2IF
INT2 pin
INT2 INTERRUPT
IEDS
[0D8
H
]
Edge selection
register
2
2
2
Interrupt
goes
active
Interrupt
latched
Interrupt
processing
Interrupt
routine
8 f
XIN
period
max. 12 f
XIN
period
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