參數(shù)資料
型號： GMS87C7216Q
廠商： Electronic Theatre Controls, Inc.
元件分類： 8位微控制器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁數(shù)： 66/121頁
文件大?。?/td> 1645K
代理商： GMS87C7216Q
GMS81C7208/7216
62
FEB. 2005 Ver 1.04
Example: Register save using push and pop instructions
General-purpose register save/restore using push and pop instruc-
tions;
17.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which has
the lowest priority order.
Interrupt vector address of BRK is shared with the vector of
TCALL 0 (Refer to Program Memory Section). When BRK inter-
rupt is generated, B-flag of PSW is set to distinguish BRK from
TCALL 0.
Each processing step is determined by B-flag as shown in Figure
17-5.
Figure 17-5 Execution of BRK/TCALL0
17.3 Multi Interrupt
If two requests of different priority levels are received simulta-
neously, the request of higher priority level is serviced. If re-
quests of the interrupt are received at the same time
simultaneously, an internal polling sequence determines by hard-
ware which request is serviced.
However, multiple processing through software for special fea-
tures is possible. Generally when an interrupt is accepted, the I-
flag is cleared to disable any further interrupt. But as user sets I-
flag in interrupt routine, some further interrupt can be serviced
even if certain interrupt is in progress.
Example:
During Timer1 interrupt is in progress, INT0 interrupt
serviced without any suspend.
TIMER1: PUSH
A
X
Y
IENH,#08H
IENL,#00H
PUSH
PUSH
LDM
LDM
EI
:
:
;
Enable INT0 only
;
Disable other
;
Enable Interrupt
:
:
LDM
LDM
POP
POP
POP
RETI
IENH,#0FFH
IENL,#0FFH
Y
X
A
;
Enable all interrupts
.
Figure 17-6 Execution of Multi Interrupt
INTxx:
PUSH
PUSH
PUSH
A
X
Y
;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.
interrupt processing
POP
POP
POP
RETI
Y
X
A
;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN
main task
interrupt
service task
saving
registers
restoring
registers
acceptance of
interrupt
interrupt return
B-FLAG
BRK
INTERRUPT
ROUTINE
RETI
TCALL0
ROUTINE
RET
BRK or
TCALL0
=0
=1
enable INT0
disable other
TIMER 1
service
INT0
service
Main Program
service
Occur
TIMER1 interrupt
Occur
INT0
EI
enable INT0
enable other
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable “EI” in the TIMER1 routine.
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