
LG Semicon
Full Page Read / Write Cycle
GM72V66841CT/CLT
CLK
CKE
CS
RAS
CAS
WE
A12/A13
Address
DQ(output)
a+2 a+3
a
a+1
.
..
Bank3
Active
Bank0
Active
Bank0
Read
Burst
Stop
Bank3
Precharge
R:b
C:a
R:a
..
DQ(input)
..
CKE
CS
RAS
CAS
WE
Address
DQ(input)
DQ(output)
A12/A13
V
IH
a
a+1
a-2
a-1
.
a+2
..
V
IH
a+2 a+3
a
a+1
.
.
..
..
..
..
R:b
C:a
R:a
.
.
..
..
..
..
a+4
a+1
a+5 a+6
a+3 a+4
a+2
a+5
Bank3
Active
Bank0
Active
Bank0
Write
Burst
Stop
Bank1
Precharge
50
DQM ,
DQMU/DQML
DQM ,
DQMU/DQML
High-Z
High-Z
Write Cycle
RAS-CAS Delay=3
CAS Latency=3
Burst Length=4
= VIH or VIL
Read Cycle
RAS-CAS Delay=3
CAS Latency=3
Burst Length=4
= VIH or VIL