參數(shù)資料
型號(hào)： GM2115
廠商： Electronic Theatre Controls, Inc.
英文描述： ANALOG INTER FACE XGA/SXGA ONPANEL LCD PANEL CONTROLLER
中文描述： 模擬國(guó)際米蘭的XGA / SXGA ONPANEL液晶顯示器控制器
文件頁(yè)數(shù)： 26/54頁(yè)
文件大?。?/td> 1339K
代理商： GM2115
***
Genesis Microchip Confidential ***
gm2115/25 Preliminary Data Sheet
June 2002
24
C2115-DAT-01B
For ADC interlaced inputs, the gm2115/25 may be programmed to automatically determine
the field type (even or odd) from the VSYNC/HSYNC relative timing. See Input Format
Measurement, Section 4.5.
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The gm2115/25 contains hundreds of test patterns, some of which are shown in Figure 13.
Once programmed, the gm2115/25 test pattern generator can replace a video source (e.g. a
PC) during factory calibration and test. This simplifies the test procedure and eliminates the
possibility of image noise being injected into the system from the source. The foreground and
background colors are programmable. In addition, the gm2115/25 OSD controller can be
used to produce other patterns.
Figure 13.
Some of gm2115/25 built-in test patterns
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The gm2115/25 has an Input Format Measurement block (the IFM) providing the capability
of measuring the horizontal and vertical timing parameters of the input video source. This
information may be used to determine the video format and to detect a change in the input
format. It is also capable of detecting the field type of interlaced formats.
The IFM features a programmable reset, separate from the regular gm2115/25 soft reset.
This reset disables the IFM, reducing power consumption. The IFM is capable of operating
while the gm2115/25 is running in power-down mode.
Horizontal measurements are measured in terms of the selected IFM_CLK (either TCLK or
RCLK/4), while vertical measurements are measured in terms of HSYNC pulses.
For an overview of the internally synthesized clocks, see section 4.1.
4.5.1 HSYNC / VSYNC Delay
The active input region captured by the gm2115/25 is specified with respect to internal
HSYNC and VSYNC. By default, internal syncs are equivalent to the HSYNC and VSYNC
at the input pins and thus force the captured region to be bounded by external HSYNC and
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