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參數(shù)資料
| 型號： | GM2115 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ANALOG INTER FACE XGA/SXGA ONPANEL LCD PANEL CONTROLLER |
| 中文描述： | 模擬國際米蘭的XGA / SXGA ONPANEL液晶顯示器控制器 |
| 文件頁數(shù)： | 21/54頁 |
| 文件大?。?/td> | 1339K |
| 代理商： | GM2115 |
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***
Genesis Microchip Confidential ***
gm2115/25 Preliminary Data Sheet
June 2002
19
C2115-DAT-01B
5. Half Reference Clock (RCLK/2) is the RCLK (see 2, above) divided by 2. Used as
OCM_CLK domain driver.
6. Quarter Reference Clock (RCLK/4) is the RCLK (see 2, above) divided by 4. Used as
alternative clock (faster than TCLK) to drive IFM.
8. ADC Output Clock (SENSE_ACLK) is a delay-adjusted ADC sampling clock, ACLK.
ACLK is derived from SCLK.
RCLK
PLL
SDDS
DDDS
/2
/4
SCLK
DCLK
RCLK/2
RCLK/4
HSYNC
IP_CLK
TCLK
Figure 8.
Internally Synthesized Clocks
The on-chip clock domains are selected from the synthesized clocks as shown in Figure 9
below. These include:
1. Input Domain Clock (IP_CLK). Max = 165MHz
2. Host Interface and On-Chip Microcontroller Clock (OCM_CLK). Max = 100MHz
3. Filter and Display Pixel Clock (DP_CLK). Max = 135MHz
4. Source Timing Measurement Domain Clock (IFM_CLK). Max = 50MHz
5. ADC Domain Clock (ACLK). Max = 165MHz.
The clock selection for each domain as shown in the figure below is controlled using the
CLOCK_CONFIG registers (index 0x03 and 0x04).
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