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參數(shù)資料
| 型號： | GM2115 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ANALOG INTER FACE XGA/SXGA ONPANEL LCD PANEL CONTROLLER |
| 中文描述： | 模擬國際米蘭的XGA / SXGA ONPANEL液晶顯示器控制器 |
| 文件頁數(shù)： | 22/54頁 |
| 文件大?。?/td> | 1339K |
| 代理商： | GM2115 |
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***
Genesis Microchip Confidential ***
gm2115/25 Preliminary Data Sheet
June 2002
20
C2115-DAT-01B
SCLK
SENSE_ACLK
IP_CLK
DCLK
IP_CLK
DP_CLK
SCLK
ACLK
OCM_CLK
RCLK/2
TCLK
IFM_CLK
TCLK
RCLK/4
Figure 9.
On-chip Clock Domains
4
4
.
.
2
2
H
H
a
a
r
r
d
d
w
w
a
a
r
r
e
e
R
R
e
e
s
s
e
e
t
t
Hardware Reset is performed by holding the RESETn pin low for a minimum of 1
μ
s. A
TCLK input (see Clock Options above) must be applied during and after the reset. When the
reset period is complete and RESETn is de-asserted, the power-up sequence is as follows:
1. Reset all registers of all types to their default state (this is 00h unless otherwise specified
in the gm2115/25 Register Listing).
2. Force each clock domain into reset. Reset will remain asserted for 64 local clock domain
cycles following the de-assertion of RESETn.
3. Operate the OCM_CLK domain at the TCLK frequency.
4. Preset the RCLK PLL to output ~200MHz clock (assumes 14.3MHz TCLK crystal
frequency).
5. Wait for RCLK PLL to Lock. Then, switch the OCM_CLK domain to operate from the
bootstrap selected clock.
6. If a pull-up resistor is installed on ROM_ADDR9 pin (see Table 16), then the OCM
becomes active as soon as OCM_CLK is stable. Otherwise, the OCM remains in reset
until OCM_CONTROL register (0x22) bit 1 is enabled.
4
4
.
.
3
3
A
A
n
n
a
a
l
l
o
o
g
g
t
t
o
o
D
D
i
i
g
g
i
i
t
t
a
a
l
l
C
C
o
o
n
n
v
v
e
e
r
r
t
t
e
e
r
r
(
(
A
A
D
D
C
C
)
)
The gm2115/25 chip has three ADC’s (analog-to-digital converters), one for each color (red,
green, and blue).
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