參數(shù)資料
型號(hào)： GC3011-CQ
文件頁(yè)數(shù)： 9/34頁(yè)
文件大?。?/td> 194K
代理商： GC3011-CQ
GRAYCHIP,INC.
- 9 -
JULY 22, 1996
GC3011 DIGITAL RESAMPLER
This document contains information which may be changed at any time without notice
The chip outputs the resampled clock on the CKOUT pin. This clock will drive up to 40 pF of load.
In a typical application the user will connect the CKOUT pin to an external clock buffer or driver chip. The
output of the driver chip is then used to drive the output clock (OCK) pin as well as any circuitry accepting
the GC3011 chip’s output data. This guarantees that the output data will be clocked out of the GC3011 chip
using the same clock edge that the follow-on circuitry uses to accept it.
The chip also generates a double rate clock (CK2X). This clock is twice the rate of the CKOUT clock
and is locked to the CKOUT clock so that the rising and falling edges of CKOUT line up with rising edges of
the CK2X.
The chip automatically adapts the clock division ratio, the number of stages in the ring oscillator and
the control voltage so as to generate a clock which matches the resampled data rate and keeps the FIFO
half full. The adaption time is typically very short (less than 2000 output clock cycles). The VCO/PLL will
then track variations in temperature, supply voltage and resampling ratio over a
±
12% range.
The user must check that the
±
12% is adequate for the application. To do this one must estimate
the maximum temperature variation, the maximum supply voltage variation and the maximum resampling
rate variation for the resampler and then use the following dependencies to estimate the adequate tracking
range. The temperature dependence of the VCO is -0.27%/C. The voltage dependence of the VCO is
18%/V at 5 volts and 40% per volt at 3.3 volts.
For example, if the temperature at adaption time is 100 C and is expected to vary
±
20 C, and if
the voltage at adaption time is 5V and is expected to vary
±
0.1V, and if the resampled data rate is expected
to change by 0.1%, then the total range required is:
VCO range =
±
(0.27
×
20 + 18
×
0.1 + 0.1) =
±
7.3%
which is well within the
±
12% allowable range.
The CLOCK control registers (see Section 4.7) allow the user to force, if necessary, the divider and
ring oscillator length settings. The VCO status register allows the user to monitor the divider and length
settings.
2.8.3
Extended VCO Range Mode
The pull range of the VCO can be extended by setting the EXTENDED_RANGE bit in the CLOCK
control registers (See Section 4.7). This mode doubles the pull range to
±
24%to allow a wider variance due
to temperature or voltage fluctuations. This mode increases the phase jitter of the VCO.
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