參數(shù)資料
型號(hào): GC3011-CQ
文件頁數(shù): 19/34頁
文件大?。?/td> 194K
代理商: GC3011-CQ
GRAYCHIP,INC.
- 19 -
JULY 22, 1996
GC3011 DIGITAL RESAMPLER
This document contains information which may be changed at any time without notice
4.2
OFFSET WORD REGISTERS
Registers 4, and 5 contain the 14 bit delay offset word. Bit 0 is the LSB, bit 13 is the MSB.
ADDRESS 4:
OFFSET BYTE 0
BIT
TYPE
NAME
DESCRIPTION
0-7
R/W
OFFSET
[0:7]
Byte 0 (least significant) of the offset
ADDRESS 5:
OFFSET BYTE 1
BIT
TYPE
NAME
DESCRIPTION
0-5
6,7
R/W
R/W
OFFSET
[8:13]
LOAD_OFFSET
Most significant 6 bits of the offset
The sync mode for loading the offset into the offset
circuit. See Table 1 in Section 4.4 for details.
If the desired delay offset is
D
, and the input sampling rate is
F
IN
, then the offset should be set to:
OFFSET
= D*
F
IN
Where
OFFSET
is a unsigned fractional value ranging from 0 to 4 and formatted as follows:
Bits 12 and 13 are the integer part of
OFFSET
and can equal 0, 1, 2, or 3. The fractional part can
take on any value.
After loading the offset delay value the user can choose, using the LOAD_OFFSET control bits, to
have it take effect immediately, or when a sync event occurs.
MSB
LSB
0
BINARY
POINT
INTEGER
FRACTION
1
2
3
4
7
8
5
6
13 12 11 10 9
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