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| 型號： | GC3011-CQ |
| 文件頁數(shù)： | 2/34頁 |
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| 代理商： | GC3011-CQ |
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GRAYCHIP,INC.
- 2 -
JULY 22, 1996
GC3011 DIGITAL RESAMPLER
This document contains information which may be changed at any time without notice
2.0
FUNCTIONAL DESCRIPTION
Fabricated in 0.7 micron CMOS technology, the GC3011 chip is a general purpose digital resampler
chip designed to accurately reduce the sample rate of the input data stream by a fractional amount ranging
from 1.0 down to 0.25. The chip includes an interpolation control block, a multi-chip synchronization and
offset circuit, a 15 tap interpolation filter, a 16 word output FIFO memory, an output clock generator and an
interpolation ratio rate-lock loop (RLL) circuit. In addition, an output multiplexor circuit allows the user to
by-pass the FIFO and output the resampled samples directly. A control interface allows the user to set the
resampling modes, resampling rate and output clocking modes.
The multi-chip sync and offset circuit allows multiple GC3011 chips to be synchronized in a
master/slave configuration. The offset portion of the circuit allows each chip’s interpolation delay to be offset
by a fixed amount relative to the other chips. The GC3011 chip accepts input rates up to 70 MHz.
The chip can operate in a fixed resampling mode where the user specifies the desired output rate,
or the chip can be configured to adapt the resampled rate to match an externally provided output clock. The
resampled data can be output synchronous to the input clock or can be output synchronous to the output
clock. When output synchronous to the input clock the samples are accompanied by a data valid flag to
indicate which samples are valid and which are invalid. When output synchronous to the output clock the
chip uses the internal 16 word FIFO to smooth the data. The output clock can be provided externally, or can
be generated within the chip using the internal oscillator which is locked to the resampled data rate.
The chip does not provide any anti-alias filtering. The user must bandlimit the input signal before it
is down-sampled by the GC3011 chip. The GC2011 digital filter chip can be used for this purpose.
Fractional upsampling can be achieved by using the GC2011 digital filter chip to up sample the
signal by a factor of two before it is downsampled by the GC3011.
On chip diagnostic circuits are provided to simplify system debug and maintenance.
The chip receives configuration and control information over a microprocessor compatible bus
consisting of an 8 bit data I/O port, a 4 bit address port, a read/write bit, and a control select strobe. The
chip’s 16 control registers (8 bits each) are memory mapped into the 4 bit address space of the control port.
2.1
CONTROL INTERFACE
The chip is configured by writing control information into sixteen control registers within the chip.
The contents of these control registers and how to use them are described in Section 4.0. The registers are
written to or read from using the
C[0:7]
,
A[0:3]
,
R/W
, and
a unique address within the chip. An external processor (a microprocessor, computer, or DSP chip) can
write into a register by setting
A[0:3]
to the desired register address, setting the
to the desired value and then pulsing
CS
low.
CS
pins. Each control register has been assigned
R/W
pin low, setting
C[0:7]
To read from a control register the processor must set
and then set
CS
low. The chip will then drive
processor has read the value from
A[0:3]
to the desired address, set
R/W
high,
C[0:7]
with the contents of the selected register. After the
it should set
CS
high. The
C[0:8]
C[0:7]
pins are turned off (high
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