參數(shù)資料
型號(hào)： GC3011-CQ
文件頁(yè)數(shù)： 5/34頁(yè)
文件大小： 194K
代理商： GC3011-CQ
GRAYCHIP,INC.
- 5 -
JULY 22, 1996
GC3011 DIGITAL RESAMPLER
This document contains information which may be changed at any time without notice
by setting the interpolation ratio to a value close to the actual ratio
1
and setting the adaption constants 2
-A
and 2
-B
, where A and B are constants ranging from 0 to 31.
These constants set the adaption rate and the tracking bandwidth of the adaption loop. These
constants can also be set to zero in order to clear the 2
process. A large value for B will slow the adaption process and will reduce the phase jitter, but will also
decrease the tracking bandwidth of the loop. The adaption time when the interpolation ratio starts at zero
-A
or 2
-B
feedback paths or to freeze the adaption
will be approximately 2
will adapt to an output rate change and if it adapts fast enough to prevent a FIFO overflow or underflow error.
B
clock cycles. The tracking bandwidth of the loop is determined by how fast the loop
Since the FIFO has a range of +/- 8 samples, the tracking range in Hz is approximately 2
clock rate
.
(3-B)
times the input
2
The constant 2
-A
is used to dampen the adaption loop to prevent ringing. The value of A should be
approximately one-half of B. Note that small values of A will introduce residual phase jitter equal to +/-
360x2
-A
degrees.
The values of A and B are application dependant. If adaption time is important, then a two-stage
adaption process may be desirable. An initial setting of B equal to 16 and A equal to 12 will allow the loop
to converge rapidly. Once the loop has converged, A and B can be set to minimize residual phase noise.
Settings between 22 and 31 for B and between 14 and 15 for A are suggested. A setting of B=22 gives a
tracking bandwidth of 128 Hz. A setting of B=31 would reduce the tracking bandwidth to about 0.25 Hz.
2.5.3
External Adaption Mode
The RLL can be adapted from an external error signal using the EIN and EVAL inputs to the chip.
In this mode the user uses an external circuit to detect resampling rate errors and drives the EIN with a 0
or a 1. A ‘1’ means increase the ratio and a‘0’ means decrease it. A high level on the EVAL signal identifies
when the EIN signal is valid. The EVAL and EIN signals are clocked into the chip on the rising edge of the
input clock.
2.5.4
The Ratio-Hold Register
The user can monitor current resampling ratio using the Ratio-Hold Register. This register captures
and holds the most significant 16 bits of the current resampling ratio when the RATIO_HOLD bit is set (See
Section 4.8). This register can be used to determine if the resampler has converged in the adaptive
interpolation mode (See Section 2.5.2 above).
1. This speeds up the adaption, but is not necessary for the adaption to work. The ratio can be set to zero if desired.
2. The chip will converge to the correct interpolation ratio outside of the tracking bandwidth, but while it is converging
the FIFO will overflow or underflow so that the data output will be corrupted until it re-converges.
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