參數(shù)資料
型號(hào)： FW323
英文描述： 1394A PCI PHY/Link Open Host Controller Interface
中文描述： 1394A端口物理層的PCI /鏈接開放主機(jī)控制器接口
文件頁數(shù)： 77/152頁
文件大?。?/td> 1625K
代理商： FW323
Agere Systems Inc.
77
Data Sheet, Rev. 2
October 2001
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Internal Registers
(continued)
Table 65. Host Controller Control Register Description
Bit
31
30
Field Name
Reserved
noByteSwapData
Type
R
RSC
Description
Reserved.
Bit 31 returns 0 when read.
This bit is used to control byte swapping during host bus accesses
involving the data portion of 1394 packets. Data is swapped if
equal to 0, not swapped when equal to 1.
Reserved.
Bits 29:24 return 0s when read.
This bit informs upper-level software that lower-level software has
consistently configured the 1394a-2000 enhancements in the link
and PHY core. When this bit is 1, generic software such as the
OHCI driver is responsible for configuring 1394a-2000 enhance-
ments in the PHY core and bit 22 (aPhyEnhanceEnable) in the
FW323. When this bit is 0, the generic software may not modify
the 1394a-2000 enhancements in the FW323 and cannot interpret
the setting of bit 22 (aPhyEnhanceEnable). This bit is initialized
from serial EEPROM.
When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the
OHCI driver can set this bit to use all 1394a-2000 enhancements.
When bit 23 (programPhyEnable) is set to 0, the software does not
change PHY enhancements or this bit.
Reserved.
Bits 21:20 return 0s when read.
Link Power Status.
This bit drives the LPS signal to the PHY core
within the FW323.
This bit is used to enable (1) or disable (0) posted writes. Software
should change this bit only when bit 17 (linkEnable) is 0.
This bit is cleared to 0 by either a hardware or software reset. Soft-
ware must set this bit to 1 when the system is ready to begin oper-
ation and then force a bus reset. This bit is necessary to keep
other nodes from sending transactions before the local system is
ready. When this bit is cleared, the FW323 is logically and immedi-
ately disconnected from the 1394 bus, no packets are received or
processed, nor are packets transmitted.
When this bit is set, all FW323 states are reset, all FIFOs are
flushed, and all OHCI registers are set to their hardware reset
values unless otherwise specified. PCI registers are not affected
by this bit. This bit remains set while the softReset is in progress
and reverts back to 0 when the reset has completed.
Reserved.
Bits 15:0 return 0s when read.
29:24
23
Reserved
R
programPhyEnable
RC
22
aPhyEnhanceEnable
RSC
21:20
19
Reserved
LPS
R
RS
18
postedWriteEnable
RSC
17
linkEnable
RSU
16
SoftReset
RSU
15:0
Reserved
R
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