參數(shù)資料
型號： FW323
英文描述： 1394A PCI PHY/Link Open Host Controller Interface
中文描述： 1394A端口物理層的PCI /鏈接開放主機控制器接口
文件頁數(shù)： 124/152頁
文件大?。?/td> 1625K
代理商： FW323
124
Agere Systems Inc.
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2
October 2001
Internal Registers
(continued)
Table 107. Isochronous Transmit Context Control Register Description
Bit
31
Field Name
cycleMatchEnable
Type
RSCU
Description
When this bit is set to 1, processing occurs such that the packet
described by the context’s first descriptor block is transmitted in the
cycle whose number is specified in the cycleMatch field (bits 30:16).
The cycleMatch field (bits 30:16) must match the low-order 2 bits of
cycleSeconds and the 13-bit cycleCount field in the cycle start packet
that is sent or received immediately before isochronous transmission
begins. Since the isochronous transmit DMA controller may work
ahead, the processing of the first descriptor block may begin slightly in
advance of the actual cycle in which the first packet is transmitted. The
effects of this bit, however, are impacted by the values of other bits in
this register and are explained in the 1394 Open Host Controller Inter-
face Specification Once the context has become active, hardware
clears this bit.
Contains a 15-bit value, corresponding to the low-order 2 bits of the
bus isochronous cycle timer register cycleSeconds field (bits 31: 25)
and the cycleCount field (bits 24:12). If bit 31 (cycleMatchEnable) is
set, then this isochronous transmit DMA context becomes enabled for
transmits when the low-order 2 bits of the bus isochronous cycle timer
register cycleSeconds field (bits 31:25) and the cycleCount field (bits
24:12) value equal this field’s (cycleMatch) value.
This bit is set by software to enable descriptor processing for the
context and cleared by software to stop descriptor processing. The
FW323 changes this bit only on a hardware or software reset.
Reserved.
Bits 14:13 return 0s when read.
Software sets this bit to cause the FW323 to continue or resume
descriptor processing. The FW323 clears this bit on every descriptor
fetch.
The FW323 sets this bit when it encounters a fatal error and clears the
bit when software resets bit 15 (run).
The FW323 sets this bit to 1 when it is processing descriptors.
Reserved.
Bits 9:5 return 0s when read.
Following an OUTPUT_LAST* command, the error code is indicated in
this field. Possible values are: ack_complete, evt_descriptor_read,
evt_data_read, and evt_unknown.
30:16
cycleMatch
RSC
15
run
RSC
14:13
12
Reserved
wake
R
RSU
11
dead
RU
10
9:5
4:0
active
Reserved
event code
RU
R
RU
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